09-01-2016 01:08 AM
I'm migrating a Vivado 2015.2 project to 2016.2 version.
My project is composed of several modules. Each module could have several Xilinx IPs. By module, a small Vivado project manages the module IPs and generates the IPs output products using "out of context per IP" option -> generation of the .dcp file for each IP. Then, my Vivado global project includes all the .dcp files for the IPs along with the modules verilog code files.
This project works fine with Vivado 2015.2 but not with Vivado 2016.2.
1. During synthesis, I got warning messages for each IP such as :
[Project 1-486] Could not resolve non-primitive black box cell 'dpram_energy' instantiated as 'u_if_cpu/u_dpram_mngt/u_dpram_energy' ["dpram_mngt.v":208].
Is that kind of warning due to Vivado 2016.2 ? Could I ignore them ?
2. During implementation, I got an error with a PLL (IP created with the clock wizard 5.3) :
[DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal u_clock_mngt/pll_nav_inst/pll_nav1_inst/inst/CLKIN1 on the u_clock_mngt/pll_nav_inst/pll_nav1_inst/inst/plle2_adv_inst/CLKIN1 pin of u_clock_mngt/pll_nav_inst/pll_nav1_inst/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
Concerning this point, I found an old forum post : https://forums.xilinx.com/t5/Implementation/Drc-23-20-Rule-violation-REQP-1712-Input-clock-driver/td-p/586641. I think that my project matchs this old post : the PLL input is a FPGA input pin that goes through IBUF and BUFG, i use .dcp file, the COMPENSATION parameter equals ZHOLD by default in my IP.
Is there a Vivado evolution that could explain that what works fine in 2015.2 version leads to an error in Vivado 2016.2 ?
Should I just override the COMPENSATION parameter to BUF_IN value in my PLL IP to obtain the same functioning than in Vivado 2015.2 ?
09-01-2016 02:32 AM - edited 09-01-2016 02:32 AM
[Project 1-486] Could not resolve non-primitive black box cell 'dpram_energy' instantiated as 'u_if_cpu/u_dpram_mngt/u_dpram_energy'
The above warning can be safely ignored. This warning is issued for IP's as the IP synthesis is run in out of context mode.
[DRC 23-20] Rule violation (REQP-1712)
Open synthesized design in 2015.2 and 2016.2 and check if the driver of PLL instance is same in both designs.
If you can upload the 2016.2 _opt.dcp file I can further check if this is tool issue or not.
09-01-2016 05:01 AM
In the synthesized design, I confirm that the driver of PLL instance is the same in 2015.2 and 2016.2 (see the attached png files, the RST name given by Vivado is different but the functionality is the same).
"If you can upload the 2016.2 _opt.dcp file I can further check if this is tool issue or not."
-> Vivado does not create a pll_nav1_opt.dcp file. I only have a pll_nav1.dcp file : is it that file you'd like me to post ?
09-01-2016 10:17 PM
What is the value of COMPENSATION property of PLL instance in 2015.2 design?
If you using Vivado GUI to create the project, you will find the _opt.dcp file at project_name.runs --> impl_1 location.
09-02-2016 12:18 AM
The COMPENSATION property of PLL instance in 2015.2 design is ZHOLD.
To be more precise, in the clocking wizard 5.1, I read ZHOLD in front of COMPENSATION but this parameter is read-only because the "allow override mode" is unchecked.
For information, in 2016.2 design, I check the "allow override mode" option and modify the COMPENSATION parameter to BUF_IN. With this setting, the implementation is successful but I can not ensure that the PLL functioning is the same as in 2015.2 design.
Concerning _opt.dcp file, I use Vivado GUI to generate the PLL IP OOC but I can not find the project_name.runs directory. I only got the following directories : project_name.cache, project_name.hw and project_name.sim.
09-02-2016 12:33 AM
It looks like you are using script mode to run implementation. I need checkpoint after opt_design phase. In your TCL include write_checkpoint command after opt_design to generate DCP file.
Is the PLL not functioning correctly in 2016.2 after change in this attribute?
09-02-2016 08:39 AM
I do not use script mode to run implementation.
I have a small Vivado project for the Xilinx IPs (and only for the Xilinx IPs).
When migrating, I opened the 2015.2 project with Vivado 2016.2 :
1. Vivado updated the project to 2016.2 version (after I accepted the migration)
2. I manually updated the Xilinx IPs (right click on the IP and tool "upgrade IP") without enabling core container
3. Then I generated the output products in OOC mode
4. I obtained the .dcp files which are refered in my global Vivado project (see my original post)
I do not know how to execute the write_checkpoint command to obtain the _opt.dcp file.
"Is the PLL not functioning correctly in 2016.2 after change in this attribute?" -> I can not answer this question at the moment. I do not know when I will be able to test the FPGA.
09-05-2016 10:03 PM
Please share 2016.2 project archive. Use file --> archive project option in vivado to archive the files.
09-06-2016 12:08 AM
09-13-2016 03:58 AM
It looks like you had shared Managed IP project. However I was looking for entire RTL project archive.
09-16-2016 01:02 AM
Sorry but I can't post my entire RTL project archive on the internet...
Could you just look at the evolutions on the clock wizard to explain this difference between Vivado 2015.2 and 2016.2 ?
If not, i will just wait until I can test the PLL on my electronic board.