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Teacher
Teacher
3,617 Views
Registered: ‎07-09-2009

Kintex, Fifos in vivado 2016.3 IP or macro

 Fifos in Kintex parts under Vivado 2016.3 ,

.

The recommendation used to be to use IP generator,

 

   a quick scan through the new docs in 2016.3 do I understand the recommended way to use fifos in HDL is not to instantiate the macro ?

 

If thats so, which I'd like to know for the coding guidelines we use internaly 

 

would this by default slow down the 'compile', as the fifos are no longer "out of context". 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

you can use IPI Block , FIFO generator core (which supports BRAM , LUTs and built in FIFO), You can also use XPM and Primitive .

You can also write your own FIFO logic .

Xilinx recommend to use IPI/IP catalog for better performance.
Thanks and Regards
Balkrishan
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Teacher
Teacher
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Registered: ‎07-09-2009

Thanks 

 

yep know of all those ways to make a fifo, 

   

Your comment about using the IP is what I have always used , 

 

Was wondering where does  UG768   page 62, stand where it says about macro instantiation.

    is that not may be implying that is the way to put fifos' into your hdl code ?

 

 

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