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Explorer
Explorer
139 Views
Registered: ‎02-17-2009

Locked IPs in a design but all IPs are up-to-date

I moved a BD design built exclusively out of Xilinx IP cores from Vivado 2019.1 to 2019.1.1 and changed the target device from xczu27 to xczu28. Now I am getting the following messages when attempting to validate it :

[BD 5-336] This command cannot be run, as the BD-design is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
design_1_auto_cc_2
design_1_xbar_9
design_1_auto_us_0
design_1_auto_us_1
design_1_auto_cc_3
design_1_auto_cc_4
design_1_auto_cc_1

These cores don't seem to be a part of the design unless they are internal to some other cores. report_ip_status says that all cores are up-to-date.

I tried to ignore this but then the implementation failed with the following:

[Project 1-682] Sub-design 'design_1.bd' is not generated for Synthesis target. Please open this sub-design and generate with synth_checkpoint_mode as 'Singular' in original project before adding it to current project.

Thanks,
/Mikhail

 

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2 Replies
Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎01-30-2019

Re: Locked IPs in a design but all IPs are up-to-date

Hi @mmatusov 

can you please have a look at the Determining why IP is locked section of the  following document

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug896-vivado-ip.pdf#page=87

Regards

Suraj C 

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Explorer
Explorer
60 Views
Registered: ‎02-17-2009

Re: Locked IPs in a design but all IPs are up-to-date

Hello @surajc ,

I resolved the problem by changing the part to a non-Zynq part first, updating all the IP cores and then back to the Zynq part I wanted and updating all the cores again. 

/Mikhail

 

 

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