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Explorer
Explorer
5,333 Views
Registered: ‎07-13-2015

MMCM allows only 7 output frequencies

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I am only able to generate 7 clocks by one MMCM. I want more than 7 clocks for my design. Do i need to use another MMCM. Is there a way so that i can generate more than 7 clocks from one MMCM only.

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Xilinx Employee
Xilinx Employee
9,970 Views
Registered: ‎08-01-2008
yes you can use multiple MMCM
check this post as well
https://forums.xilinx.com/t5/General-Technical-Discussion/How-to-Synchronize-clocks-between-multiple-MMCM/td-p/567146
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
mmcm supports Output clock frequencies up to seven maximum only . you can use clock divider circuits
Thanks and Regards
Balkrishan
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Explorer
Explorer
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Registered: ‎07-13-2015

Is it ok to use two MMCM's.

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Xilinx Employee
Xilinx Employee
9,971 Views
Registered: ‎08-01-2008
yes you can use multiple MMCM
check this post as well
https://forums.xilinx.com/t5/General-Technical-Discussion/How-to-Synchronize-clocks-between-multiple-MMCM/td-p/567146
Thanks and Regards
Balkrishan
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Moderator
Moderator
5,285 Views
Registered: ‎07-21-2014

@hulk789

 

You need to use multiple MMCMs if your design have more clocks. Also, refer the 7 series clocking user guide for more details:

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

Thanks,
Anusheel
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Teacher
Teacher
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Registered: ‎03-31-2012
I'm curious why more than 7 clocks are necessary, would you mind describing the design a little?
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Explorer
Explorer
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Registered: ‎07-13-2015

I have input 10Mhz clock.

I want to generate 40Mhz clocks with phase 0 , 180

20 Mhz clocks with phase 0,90,180,270

10Mhz clocks with phase 0,45,90,135,180,225,270,315

If i give clkin(same clk) to two MMCM will they be synchronized 

 

When i tried to use 2 MMCM

Issues faced:

1. [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 13 logical ports have no user assigned(This is for the clkin signal)

2.Not enough BUFG's inside FPGA

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