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Visitor
Visitor
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Registered: ‎12-28-2018

Make interface for RTL module

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Hi, I defined a module using verilog. In Vivado project, I added the module to block design. In the block, AXI interfaces are correctly recognized and grouped into a "+" sign in the GUI. However the GPIO interface is not recognized, though I named the ports with suffixes of "TRI_I,TRI_O,TRI_T". How can I make interface in such case? I know that if I package the module into an IP, there are options to make interface. But that makes the project scattered. I want to reference RTL modules directly. Thank you. 

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Moderator
Moderator
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Registered: ‎01-16-2013

@cueekoo 

 

IO interfaces are not defined in Language Templates so I don't think they are available/supported for your flow:

image.png

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
1,125 Views
Registered: ‎01-16-2013

@cueekoo 

 

IO interfaces are not defined in Language Templates so I don't think they are available/supported for your flow:

image.png

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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Contributor
Contributor
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Registered: ‎07-24-2009

Vivado 2019.1 recognizes following constructs:

(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_I" *)
(* X_INTERFACE_MODE = "master GPIO" *)
input  [WIDTH-1:0] gpio_io_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_O" *)
output [WIDTH-1:0] gpio_io_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_T" *)
output [WIDTH-1:0] gpio_io_t;
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