Make interface for RTL module

[cueekoo]

Hi, I defined a module using verilog. In Vivado project, I added the module to block design. In the block, AXI interfaces are correctly recognized and grouped into a "+" sign in the GUI. However the GPIO interface is not recognized, though I named the ports with suffixes of "TRI_I,TRI_O,TRI_T". How can I make interface in such case? I know that if I package the module into an IP, there are options to make interface. But that makes the project scattered. I want to reference RTL modules directly. Thank you. 

[syedz · Accepted solution]

@cueekoo 

IO interfaces are not defined in Language Templates so I don't think they are available/supported for your flow:

--Syed

[5506273]

Vivado 2019.1 recognizes following constructs:

(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_I" *)
(* X_INTERFACE_MODE = "master GPIO" *)
input  [WIDTH-1:0] gpio_io_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_O" *)
output [WIDTH-1:0] gpio_io_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio_rtl:1.0 GPIO TRI_T" *)
output [WIDTH-1:0] gpio_io_t;