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Visitor lee.lemay
Visitor
9,898 Views
Registered: ‎07-04-2014

Migrating EDK IP to Vivado for AD-FMCJESDADC1-EBZ reference design

I am attempting to migrate the reference design for the AD-FMCJESDADC1-EBZ to Vivado. The reference design can be found here:

http://wiki.analog.com/resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz

 

I am following the steps in chapter 5 of UG940, using the "Create and Package IP" too, but I run into a problem when I try to package one of the components. It gives a critical error:

 

[IP_Flow 19-2976] File Group 'xilinx_anylanguagesynthesis (Synthesis)': The referenced subcore "xilinx.com:ip:axi_master_lite:1.00.a" is not found in the IP catalog.

I tried to find documentation on the axi_master_lite core, and it seems to say that it is included in Vivado. However, it does not show up in the IP Catalog. I tried modifying all of the references to version 3.00, since that is the most current release, and I got the error to change to:

 

[IP_Flow 19-2976] File Group 'xilinx_anylanguagesynthesis (Synthesis)': The referenced subcore "xilinx.com:ip:axi_master_lite:3.00.a" is not found in the IP catalog.

Does anyone know how to fix this?

 

Thanks,

Lee

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4 Replies
Xilinx Employee
Xilinx Employee
9,895 Views
Registered: ‎07-01-2010

Re: Migrating EDK IP to Vivado for AD-FMCJESDADC1-EBZ reference design

Hi,
Looks like vivado was not able to find the IP .Is the IP added to the project repositories?
Please refer to the latest migration details for migration.
Migration guide:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_3/ug911-vivado-migration.pdf
Regards,
Achutha
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Visitor lee.lemay
Visitor
9,879 Views
Registered: ‎07-04-2014

Re: Migrating EDK IP to Vivado for AD-FMCJESDADC1-EBZ reference design

It seems true that the ip core xilinx.com:ip:axi_master_lite:1.00.a is not being seen by Vivado.

I also modified the project to find v3.00.a, since that is the most recent release, and it wasn't seen either. My question is, why isn't it being seen by Vivado, and how do I fix it?

 

The core seems to be a xilinx core - it's documentation can be found here:

http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/ip_documentation/embedded_processing/processor_interface/axi_master_lite.html

 

The pdf file lists vivado as part of its tested design flows:

http://www.xilinx.com/support/documentation/ip_documentation/axi_master_lite/v3_0/pg161-axi-master-lite.pdf

 

Why isn't it already included in Vivado?

 

I appreciate your help!

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Xilinx Employee
Xilinx Employee
9,865 Views
Registered: ‎07-01-2010

Re: Migrating EDK IP to Vivado for AD-FMCJESDADC1-EBZ reference design

Hi,

 

Every IP/custom IP generated is associated with the .xml and the user is supposed to source the .xml so that Vivado picks the IP .

 

Can you  try the below steps and see if that helps?

1.Open Vivado Project

2.Click on Tools -->Project Settings

3.Click on IP 

4.Click on Add Repository and source the IP .xml file and click OK.

5.Once the .xml file is source and the IP is added you should see the IP in the IPin Selected Repository tab.

6.After the IP is seen in the repository window, open the block design and see if you can add the IP.

 

Regards,

Achutha

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Xilinx Employee
Xilinx Employee
9,852 Views
Registered: ‎07-01-2010

Re: Migrating EDK IP to Vivado for AD-FMCJESDADC1-EBZ reference design

Hi,

Do you have a chance to follow the steps?
Do you still see the issue?

Regards,
Achutha
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