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Visitor aruns0201
Visitor
130 Views
Registered: ‎10-30-2019

Module names in schematic is visible for design synthesised using encrypted files

Hi All, 

 

 

I have Encrypted design files using Vivado 2018 , 

I am generating this design files using the below conditional right

`pragma protect control decryption=(xilinx_activity==simulation) ? "false" : "true"

 

After synthesis is completed on the encrypted design , the schematic view of the netlist shows all the module names of top files and also sub blocks , and it also has all the details of the design , how to avoid this? since the main aim of encryption is to prevent the Ip consumer from knowin the internal details.

 

below are the other xilinx toolbox conditional rights I am using - 

`pragma protect control xilinx_configuration_visible = "false"
`pragma protect control xilinx_enable_modification = "false"
`pragma protect control xilinx_enable_probing = "false"
`pragma protect control xilinx_enable_netlist_export = "true"
`pragma protect control xilinx_enable_bitstream = "true"
`pragma protect control decryption=(xilinx_activity==simulation) ? "false" : "true"

 

 

Thanks

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1 Reply
Moderator
Moderator
108 Views
Registered: ‎01-16-2013

Re: Module names in schematic is visible for design synthesised using encrypted files

@aruns0201 

 

Can you try in 2019.1 version? This has xilinx_schematic_visibility property. Check Table 6-2 in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1118-vivado-creating-packaging-custom-ip.pdf#page=95 

 

--Syed

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