Hi,
I am using Artix-7 FPGA, and I use the 2018.3 vivado version.
I followed UG994 to add a RTL module in my block design. Below are the steps,
- Add the source file into the project
- Open the Block Design, and choose Add Module in right-click menu, and choose the Verilog source file. Then a RTL block is added in the BD successfully.
- Do the connection between the RTL block and other IP modules.
- Generate Output Products via OOC per Block Design
- Run Synthesis
After synthesis, I found on the top of GUI there is a yellow bar with a warning like the below picture,
I am not sure if this warning can be ignored.
When I click the refresh, and after generating the BD, this warning appears again.
I run the report_ip_status in tcl console, and it showed the RTL referenced module as below,
I upgrade the module in IP status while the warning exited all the same.
Every time I run the synthesis, the BD will be generated again which takes a lot of time.
I have already create a HDL wrapper, but the HDL wrapper was generated when I generate the BD OOC, isn’t it?
And I also instantiated the wrapper in top verilog file.
Could you help to check my steps if something wrong or I missed? Or could you give some suggestion on solving it?
