10-10-2019 02:36 AM
Hi，I am trying to add a RTL module into Block Design，and after I generated the BD via OOC，it successful but it prompt that "Modul references are out-of-date. Refresh changed modules".
I think I encounter the issue as https://forums.xilinx.com/t5/Design-Entry/2017-2-quot-Refresh-changed-modules-quot-not-cliclable/m-p/792412#M14434 but I don't understand the solution. How can I solve it? Thanks in advance.
10-10-2019 02:42 AM
Hi @yinglu2 ,
After addignRTL module. Create a wrapper around the design and set that as top and then try. Also please check the below post:
10-10-2019 06:51 PM
Hi，the original BD consists of the IP from IP Catalog，and I want to add a RTL module in BD. I found I couldn't generate a HDL wrapper for this RTL module. I couldn't set it as the TOP either, How can I do it?
10-10-2019 07:17 PM
Hi, in Xilinx UG944, I think the HDL Wrapper is generated for BD. I have generated the HDL wrapper for the whole BD, but I still get the out-of-date warning.
And I found I didn't generate the .xci file, in UG944 there is a .xci file for the RTL module in the guide,
However, in my design, it showed "Module Reference Wrapper" as below.
BTW, may I know can I make the RTL module OOC?