cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
509 Views
Registered: ‎06-24-2019

Module references are out-of-date

 

Hi,I am trying to add a RTL module into Block Design,and after I generated the BD via OOC,it successful but it prompt that "Modul references are out-of-date. Refresh changed modules".

I think I encounter the issue as https://forums.xilinx.com/t5/Design-Entry/2017-2-quot-Refresh-changed-modules-quot-not-cliclable/m-p/792412#M14434   but I don't understand the solution. How can I solve it? Thanks in advance.

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
505 Views
Registered: ‎05-22-2018

Hi @yinglu2 ,

After addignRTL module. Create a wrapper around the design and set that as top and then try. Also please check the below post:

https://forums.xilinx.com/t5/Design-Entry/Vivado-Block-Design-error-when-a-RTL-block-instantiates-catalog/td-p/755285 

 

Thanks,

Raj.

0 Kudos
Highlighted
Contributor
Contributor
452 Views
Registered: ‎06-24-2019

 

Hi,the original BD consists of the IP from IP Catalog,and I want to add a RTL module in BD. I found I couldn't generate a HDL wrapper for this RTL module. I couldn't set it as the TOP either, How can I do it?

0 Kudos
Highlighted
Contributor
Contributor
444 Views
Registered: ‎06-24-2019

 

Hi, in Xilinx UG944, I think the HDL Wrapper is generated for BD. I have generated the HDL wrapper for the whole BD, but I still get the out-of-date warning.

And I found I didn't generate the .xci file, in UG944 there is a .xci file for the RTL module in the guide,

Screen Shot 2019-10-11 at 10.11.08 AM.png

However, in my design, it showed "Module Reference Wrapper" as below.

Screen Shot 2019-10-11 at 10.13.03 AM.png

BTW, may I know can I make the RTL module OOC?

0 Kudos