04-03-2018 11:08 PM - edited 04-04-2018 01:37 AM
I am running an implementation of a project with customized DDR4 MIG and encountered the following two errors:
Since I haven't explicitly defined the GND signals, how do I resolve this MDRV issue?
The implementation is not done yet and hence I can't even open the elaborated design.
04-03-2018 11:13 PM
Which vivado version are you using? Open the synthesized design and check the schematic
04-04-2018 10:09 PM
Im using v2017.3
A differential clock was actually used in the project by updating the MIG configuration to 'no buffer'.
I came acroos the following from the UltraScale Architecture-Based FPGAs Memory IP v1.4 LogiCORE IP Product Guide:
does this throw light on how I can remove the multiple driver nets error?