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Visitor adijoshitha
Visitor
1,103 Views
Registered: ‎03-26-2018

Multiple Driver Nets- for GND

Hi,

 

I am running an implementation of a project with customized DDR4 MIG and encountered the following two errors:

  

 

Capture.PNG

Since I haven't explicitly defined the GND signals, how do I resolve this MDRV issue?

 

The implementation is not done yet and hence I can't even open the elaborated design.

 

Thanks.

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2 Replies
Moderator
Moderator
1,098 Views
Registered: ‎01-16-2013

Re: Multiple Driver Nets- for GND

@adijoshitha,

 

Which vivado version are you using? Open the synthesized design and check the schematic

 

--Syed

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Visitor adijoshitha
Visitor
1,050 Views
Registered: ‎03-26-2018

Re: Multiple Driver Nets- for GND

@syedz

 

Im using  v2017.3

 

A differential clock was actually used in the project by updating the MIG configuration to 'no buffer'.

 

I came acroos the following from the UltraScale Architecture-Based FPGAs Memory IP v1.4 LogiCORE IP Product Guide:

 

Capture2.PNG

 

 

does this throw light on how I can remove the multiple driver nets error?

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