03-23-2021 12:26 PM
What I'd like to share today is perhaps my greatest Xilinx hack ever. Its the journey to create an architecture-independent IP core that automatically time-stamps each build, and makes that time stamp available in firmware.
Along the way, I had to learn the answers to many other questions, like: "How do I create a user-IP with parameter propagation enabled?", "How do I get the time value automatically at build time?", "How do I have Vivado change parameters of IP at validation time?", etc. I will share my journey here in the hopes that it will help other people facing similar brick walls.
A little back story...
All of my builds needs timestamps, which will serve also to uniquely identify builds. The Zynq Processor needs to be able to read this value from firmware to know which firmware load it is dealing with. After searching the forums for help and finding some fun discussions , I decided to have a go at it myself. 3 days later I crawled out of my office with a solution.
So here's what it takes.
You may be wondering why I chose to split up BUILD_TIME_STR and BUILD_DATE_STR. The reason is because these are really present just to give user feedback. With these, you can open up the IP core and see what the last build stamp was, in human readable format. However, the amount of space that Vivado will give you for a parameter string in the IP GUI is limited. I had to split it up to be able to view it all.
The other failed attempts
Before reaching this solution, I tried several other things:
03-23-2021 12:38 PM
Well done you
it shows the ingenuity of humans to over come,
Its just a pity that AMD / Xilinx after all these decades of us asking has not, unlike other companies, added the ability to easily pass in a time / date / version number,
before some one says , but you can,
yes the Xilinx answer is to use a fully TCL driven batch design build !!
As some one once said, to paraphrase, given enough random TCL you can do anything !!!!!