10-10-2011 11:38 PM
It has been several years since I have written VHDL and I used a mixed set of tools back then. I am now using ISE 13.2 to try to come back up to speed. As an example, I created a D flipflop with asynchronous set. In another file I am trying to implement a shift register (I know this isn't the simplest way to go - I'm just trying to learn how to handle hierarchy.) Next I want to modify the shift register to implement a LFSR. I've inlcuded my code for reference. It does simulate in Isim, but the outputs are undefined. I'm not sure I am using signals correctly or that I am referencing the component correctly. Can someone help? As an aside, i read in the forum that async sets and resets were "bad." Why?
10-11-2011 02:29 AM
10-11-2011 06:39 AM
Can you post the code for lsfr3? Also you might want to post a screen shot from ISIM
showing the inputs and outputs (even if they are 'U'). Usually undefined outputs mean
you didn't initialize everything they depend on at the start of simulation.
One thing I noticed in your D FF code is that it doesn't match the standard template
for a D FF, and when using asynchronous set or reset this can confuse XST:
architecture Behavioral of dff_set is
if set='1' then
elsif rising_edge(clk) then
-- else -- This else clause does nothing for simulation
-- q<=q; -- and can confuse XST. q <= q; is implied.
10-11-2011 08:35 AM
>> "async sets and resets were "bad." Why?"
> Because in most Xilinx architectures, synchronous resets use less CLB resources.
Async sets and resets are "bad" because differences in the timing of the path may cause different parts of the design to come out of reset before other parts. A synchronous set/reset will only happen on the clock edge allowing for the design to come out of reset correctly 100% of the time.
There is no difference in the CLB resources used.
10-11-2011 08:59 AM
If the reset is applied to the "async reset" input of a flip-flop, but the signal itself is released
synchronously to the clock, then it should be as good as a synchronous reset. One issue is
that by default, the timing analyzer ignores asynchronous set/reset paths, and so the timing
from release of reset is not checked for meeting setup to the next clock edge.
10-11-2011 02:19 PM
Thanks to all for the explanation about sync sets and resets-it makes sense. As for the undefined state of my outputs, in my numerous edits, I had failed to connect the output signals to the internal signals.
10-11-2011 02:22 PM
Yeah, one of the VHDL books I have made the default assignment q<=q, and pushed it as a good practice-I believe it was the Skahill book from Cypress.
10-11-2011 02:51 PM
An unconnected signal should have been undriven 'Z' rather than unknown 'U'
Anyway glad to see you're out of the woods. Interestingly that flip-flop
description with the else q <= q clause has cropped up on these forums
before. Maybe others are using their dusty VHDL texts rather than browsing
the language templates in ISE.