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Visitor jamesburrell
Visitor
6,434 Views
Registered: ‎10-10-2011

Newbie Question about hierarchial Design

Hi All,

 

It has been several years since I have written VHDL and I used a mixed set of tools back then.  I am now using ISE 13.2 to try to come back up to speed.  As an example, I created a D flipflop with asynchronous set.   In another file I am trying to implement a shift register (I know this isn't the simplest way to go - I'm just trying to learn how to handle hierarchy.)  Next I want to modify the shift register to implement a LFSR.  I've inlcuded my code for reference.  It does simulate in Isim, but the outputs are undefined.  I'm not sure I am using signals correctly or that I am referencing the component correctly.  Can someone help?  As an aside, i read in the forum that async sets and resets were "bad."  Why?

 

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7 Replies
Teacher rcingham
Teacher
6,427 Views
Registered: ‎09-09-2010

Re: Newbie Question about hierarchial Design

"async sets and resets were "bad." Why?"

Because in most Xilinx architectures, synchronous resets use less CLB resources.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Professor
Professor
6,425 Views
Registered: ‎08-14-2007

Re: Newbie Question about hierarchial Design

Can you post the code for lsfr3?  Also you might want to post a screen shot from ISIM

showing the inputs and outputs (even if they are 'U').  Usually undefined outputs mean

you didn't initialize everything they depend on at the start of simulation.

 

One thing I noticed in your D FF code is that it doesn't match the standard template

for a D FF, and when using asynchronous set or reset this can confuse XST:

 

architecture Behavioral of dff_set is
begin
  process(clk,set) begin
    if set='1' then
      q<='1';
    elsif rising_edge(clk) then
      q<=d;
--    else     -- This else clause does nothing for simulation
--      q<=q;  -- and can confuse XST.  q <= q; is implied.
    end if;
  end process;
end Behavioral;

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
6,422 Views
Registered: ‎01-03-2008

Re: Newbie Question about hierarchial Design

>> "async sets and resets were "bad." Why?"
> Because in most Xilinx architectures, synchronous resets use less CLB resources.

 

Async sets and resets are "bad" because differences in the timing of the path may cause different parts of the design to come out of reset before other parts.  A synchronous set/reset will only happen on the clock edge allowing for the design to come out of reset correctly 100% of the time.

 

There is no difference in the CLB resources used.

------Have you tried typing your question into Google? If not you should before posting.
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Professor
Professor
6,419 Views
Registered: ‎08-14-2007

Re: Newbie Question about hierarchial Design

If the reset is applied to the "async reset" input of a flip-flop, but the signal itself is released

synchronously to the clock, then it should be as good as a synchronous reset.  One issue is

that by default, the timing analyzer ignores asynchronous set/reset paths, and so the timing

from release of reset is not checked for meeting setup to the next clock edge.

 

-- Gabor

-- Gabor
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Visitor jamesburrell
Visitor
6,416 Views
Registered: ‎10-10-2011

Re: Newbie Question about hierarchial Design

Thanks to all for the explanation about sync sets and resets-it makes sense.  As for the undefined state of my outputs, in my numerous edits, I had failed to connect the output signals to the internal signals.

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Visitor jamesburrell
Visitor
6,413 Views
Registered: ‎10-10-2011

Re: Newbie Question about hierarchial Design

Yeah, one of the VHDL books I have made the default assignment q<=q, and pushed it as a good practice-I believe it was the Skahill book from Cypress.

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Professor
Professor
6,410 Views
Registered: ‎08-14-2007

Re: Newbie Question about hierarchial Design

An unconnected signal should have been undriven 'Z' rather than unknown 'U'

 

Anyway glad to see you're out of the woods.  Interestingly that flip-flop

description with the else q <= q clause has cropped up on these forums

before.  Maybe others are using their dusty VHDL texts rather than browsing

the language templates in ISE.

 

Regards,

Gabor

-- Gabor
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