10-03-2018 03:18 AM
I want to package current design as an IP for a future use, but i would like to have generic parameters for for example AXI Data/ID width (already have two external AXI interfaces in my IP). Is there a way to do that? Because i cant find anything. I guess, I can't do it manually, by changing the design wrapper file and so on, because some Xilinxs IPs i am using are closed, so i cant edit them.
10-03-2018 03:34 AM
You can modify and edit the Xilinx IP. Check this Answer record:
Also for parameters refer to the below link:
10-03-2018 04:06 AM
Hi @syedz ,
thanks fot the answer, but to be sure if we are understanding each other correctly: I am wanting to package current design as IP. This IP, among other ports has two AXI4 busses. I would like to pack this design with generic parameters for AXI bus, to have a possibility to change ID/DATA width in the future. I know, that generally I can modify Xilinxs IP, I did it from BDE, but, i would like to have parametrized AXI as an interface and to propagate those parameters deeper into used Xilinx IPs as well. I read the answer, but i think this is not related to my problem (am I correct?). I know about parameters when packaging custom ip, but there are no parameters in created in Vivado HDL wrapper, so no parameters are available in IP packager.
12-05-2019 02:41 AM