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Visitor
Visitor
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Registered: ‎06-27-2013

Packaging current project as IP, with generic parameters

Hello,

[vivado 2017.4]

I want to package current design as an IP for a future use, but i would like to have generic parameters for for example AXI Data/ID width (already have two external AXI interfaces in my IP). Is there a way to do that? Because i cant find anything. I guess, I can't do it manually, by changing the design wrapper file and so on, because some Xilinxs IPs i am using are closed, so i cant edit them.

 

Regards

Y

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Moderator
Moderator
897 Views
Registered: ‎01-16-2013

Re: Packaging current project as IP, with generic parameters

@yourand

 

You can modify and edit the Xilinx IP. Check this Answer record:

https://www.xilinx.com/support/answers/57546.html

 

Also for parameters refer to the below link: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1118-vivado-creating-packaging-custom-ip.pdf#page=54

 

--Syed

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Visitor
Visitor
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Registered: ‎06-27-2013

Re: Packaging current project as IP, with generic parameters

Hi @syedz ,

thanks fot the answer, but to be sure if we are understanding each other correctly: I am wanting to package current design as IP. This IP, among other ports has two AXI4 busses. I would like to pack this design with generic parameters for AXI bus, to have a possibility to change ID/DATA width in the future. I know, that generally I can modify Xilinxs IP, I did it from BDE, but, i would like to have parametrized AXI as an interface and to propagate those parameters deeper into used Xilinx IPs as well. I read the answer, but i think this is not related to my problem (am I correct?). I know about parameters when packaging custom ip, but there are no parameters in created in Vivado HDL wrapper, so no parameters are available in IP packager. 

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Adventurer
Adventurer
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Registered: ‎06-04-2019

Re: Packaging current project as IP, with generic parameters

Hi @yourand  ,

Did you find a solution to your problem?

Thanks,
Bhavanithya Thiraviaraja
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