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Observer chika
Observer
424 Views
Registered: ‎05-25-2019

Partition Definition on Custom IP inside block diagram

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Hi All,

im getting really confused how to add custom ip inside a block diagram and then make it reconfiguratble? if i right click on a custom IP in the sources window and click "Create partition Definition" it brings up the error message below. I cannot wrap it in a HDL wrapper, (or how do i wrap it when it is in a block design?).. i know there is a mention of not being able to make IP reconfigurable.. but i dont understand how to make custom IP reconfigurable?

Untitled.jpg

 

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Xilinx Employee
Xilinx Employee
353 Views
Registered: ‎02-27-2019

回复: Partition Definition on Custom IP inside block diagram

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This is OK:
             Top
               .
              +...your module(RM)
               .
              +...block design
                          .
                         +...other IP
This is NOT OK:
            Top
              .
             +...block design
                         .
                        +...your module(RM)
                         .
                        +...other IP

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9 Replies
Xilinx Employee
Xilinx Employee
407 Views
Registered: ‎02-27-2019

回复: Partition Definition on Custom IP inside block diagram

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Hi @chika ,

In fact, defining reconfigurable partitions has limitaions. Please refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug909-vivado-partial-reconfiguration.pdfpage 52.

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Observer chika
Observer
401 Views
Registered: ‎05-25-2019

回复: Partition Definition on Custom IP inside block diagram

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Thanks @yangc . i have seen this page. So i guess the question is then: how do i bolt my custom IP onto a wrapper that contains a block diagram for the rest of my design.. and then make "my IP" configurable ?

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Xilinx Employee
Xilinx Employee
394 Views
Registered: ‎02-27-2019

回复: Partition Definition on Custom IP inside block diagram

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Please refer to https://forums.xilinx.com/t5/Vivado/Module-with-Block-Designs-type-of-sources-in-its-hierarchy/m-p/959895.

 

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Observer chika
Observer
388 Views
Registered: ‎05-25-2019

回复: Partition Definition on Custom IP inside block diagram

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k so let me get this straight.. "Block Diagrams cannot be set as RMs." so.. if i want to plug my IP.. even if i used HDL source only .. and connected it inot an AXI interconnect.. that is part of a higher block diagram.. i cannot do this??

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Observer chika
Observer
387 Views
Registered: ‎05-25-2019

回复: Partition Definition on Custom IP inside block diagram

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sorry type ' Modules within  Block Diagrams cannot be set as RMs" .. 

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Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎02-27-2019

回复: Partition Definition on Custom IP inside block diagram

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What's meaning of higher block diagram? You can't set any modules as RM in block design. But if your module outside connect with block design , it(your module) can be set as RM.

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Observer chika
Observer
365 Views
Registered: ‎05-25-2019

回复: Partition Definition on Custom IP inside block diagram

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Ok so:

 

This is OK:

--> Module --> block degisn --> other IP

 

This is NOT OK:

--> block design --> other IP + module

 

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Xilinx Employee
Xilinx Employee
354 Views
Registered: ‎02-27-2019

回复: Partition Definition on Custom IP inside block diagram

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This is OK:
             Top
               .
              +...your module(RM)
               .
              +...block design
                          .
                         +...other IP
This is NOT OK:
            Top
              .
             +...block design
                         .
                        +...your module(RM)
                         .
                        +...other IP

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Observer chika
Observer
340 Views
Registered: ‎05-25-2019

回复: Partition Definition on Custom IP inside block diagram

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Ok thankyou.

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