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1,031 Views
Registered: ‎10-15-2018

Problem importing ReedMullerBasis_LUT_sp_r11_d32 from ISE to Vivado

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Hi,

We are porting a project from ISE to Vivado.

The project uses LogicCore IP - ReedMullerBasis_LUT_sp_r11_d32

When I try to import it into Vivado, I get an error-

[Project 1-160] Problems encountered while importing IP 'blk_mem_gen_v7_3'. Fail reasons:-

Failed to import IP '/home/saiuser/Documents/BhawandeepSIngh/XilinxISE/Projects/pusch_original/Source/virtex6_lib/ReedMullerBasis_LUT_sp_r11_d32/blk_mem_gen_v7_3.xco'. Import is not supported for this IP.

What am I doing wrong here ?

Thanks and sincerely

Bhawandeep Singh

 

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998 Views
Registered: ‎11-07-2018

Hello Bhawandeep,

When importing from ISE to Vivado the definitions don't get transferred. You will have to do the following steps on Vivado.

1 Go to Project Settings.

2. The General Setting Window will have a section for Language Options.

3. Click on "..." of the Verilog Options.

4. A new window will pop up. 

5. Under Defines click the + button and add FPGA in the Name tab. 

6. Apply the new settings and synthesis the project.

The errors will be solved using the steps above. 

 

Hope this helps.

-Vanshika 

View solution in original post

1 Reply
999 Views
Registered: ‎11-07-2018

Hello Bhawandeep,

When importing from ISE to Vivado the definitions don't get transferred. You will have to do the following steps on Vivado.

1 Go to Project Settings.

2. The General Setting Window will have a section for Language Options.

3. Click on "..." of the Verilog Options.

4. A new window will pop up. 

5. Under Defines click the + button and add FPGA in the Name tab. 

6. Apply the new settings and synthesis the project.

The errors will be solved using the steps above. 

 

Hope this helps.

-Vanshika 

View solution in original post