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Participant lanxiang.ben
Participant
7,731 Views
Registered: ‎04-08-2014

Problem of FIFO generated by Vivado2013.4

Hi All

    The configuration fo my FIFO is shown as ancessory.My rd_clk and wr_clk are all 250M,but asynchronous.

    Now, on board by chipscope,I found that the din and corresponding dout is not the same,there is no  timing problem during implimemtation.I want to know:

    1. What is the possible reason about the problem?

    2. Whether the ability of the FIFO could touch the performance?

BR

lanxiang

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Xilinx Employee
Xilinx Employee
7,725 Views
Registered: ‎02-06-2013

Re: Problem of FIFO generated by Vivado2013.4

Hi

 

can you check if the issue is seen in simulation also.

 

Are you driving the write and read signals properly considering empty and full signals.

 

Can you attach the chipscope captures showing the issue.

 

 

Regards,

Satish

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