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Visitor
Visitor
5,015 Views
Registered: ‎12-12-2008

Programmable Full Flag of generated FIFO is asserted to late

Hi all,

 

with FIFO Generator v4.3 I generated I FIFO with the following properties:

 

  • distributed RAM
  • independent clocks
  • constant single programmable full threshold
  • normal read mode (no FWFT)

 

The user guide says on pg. 57 about the programmable full flag:

 

Note: If a write operation occurs on a rising clock edge that causes the number of words to meet or
exceed the programmable full threshold, then the programmable full flag will assert on the next rising
clock edge. The deassertion of the programmable full flag has a longer delay, and depends on the
relationship between the write and read clocks.

 

Table 4-18 provides the same information.

 

In simulation however, the  flag is asserted with a latency of five clock cycles. An FPGA programmed with a design using this FIFO verifys the simulated behaviour. Is the doumentation wrong here or am I?

 

May the latency change through read operations? (I don't mean the deassertion of the programmable full flag here)

 

Thanks for your answers in advance!

 

regards,

David 

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Xilinx Employee
Xilinx Employee
4,852 Views
Registered: ‎04-11-2008

just a suggestion, maybe you are looking at the full flag instead of the prog_full flag. That would explain a latency difference.

 

JB

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Visitor
Visitor
4,850 Views
Registered: ‎12-12-2008

Thank you for your answer. I'm definitely looking at the programmable full flag. The "normal" full flag shouldn't be delayed neither, should it?
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