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faberr
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Registered: ‎04-07-2015

RE: Ultrascale "Built-In-Fifo" prog_full value for a 4096x64 Fifo is limited from (2050 - 4094)

Xilinx Support,

 

I have existing IP (Eg. *.ngc files) such as a (4096x64 Built-In Fifo), which was created with ISE. In ISE, a prog_full_assert

value of "1900", was a valid selection for this FIFO. I am now migrating this design to an UltraScale FPGA.

 

Since the *.ngc files are not supported in Vivado 2014.3 and later, I have to either re-generate this IP, or use the

convert_ngc command. In Vivado 2016.1,  the Vivado IP-Core generator limits prog-full value of a 4096 deep "Built-In-FIFO"

to a range of  2050-4094. In ISE, a value for 1900 was a valid selection. Since I could not re-create this IP with a prog-full

value of 1900, I decided to try the convert_ngc command.

 

If I use the convert_ngc command on this design, Vivado reports that my *.ngc file was successfully converted to a *.edn file.

In the *.edn file, this parameter is set as below:

 

c_prog_full_thresh_assert_val=1900

 

Question:

When I build the FPGA, will the prog_full output pin of this (4096x64 Built-In-Fifo) be asserted HIGH at a value of 1900?

 

Thanks,

Roy

 

 

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faberr
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Registered: ‎04-07-2015

I just noticed that in Vivado 2014.2, which uses "FIFO Generator 12.0", the valid prog_full range for this FIFO is 5-4095, while In
Vivado 2016.1, which uses "FIFO_Generator 13.1" the valid range
is only 2050-4094.
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