08-23-2018 03:01 PM
I have a legacy RTL (verilog) file which I need to instantiate in a block design as RTL module. I cannot do this because this RTL file embeds six instances of a wizard generated multiplier as in below..
TstMult i_mult_11 (.CLK(clk),.A(var1),.B(var2),.P(prod));
How do I get around this? Should I package the RTL file as an IP? (can a packaged IP contain another IP?) Or is there some other technique?
Thanks a lot.
08-23-2018 11:00 PM
Just write the multipliers in RTL and get rid of the wizard generated blocks. Vivado synthesizer can infer multipliers and the code is also much easier to maintain and read.
If you really need to do the instantiation with unchanged code you have to package the whole thing instantiating the multipliers if you have Vivado 2016.4 or older. In 2017.1 or later there is support for XCI Inferencing which should support multipliers (see UG994 XCI Inferencing chapter) , though I did not do a test design to test this.