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Visitor finbarrlong
Visitor
494 Views
Registered: ‎06-26-2014

Re: Implementation - Vivado 2017.4 - merging 3'rd party EDIF netlists in a wrapper file.

Thanks Anusheel

 

Whilst the EDIF stub flow does work (thanks again) , I could not get the post synthesis flow to work.

I could not link the "top level" wrapper file with Verilog netlists.

 

Vivado Commands

       link_design -name netlist_1
              [Project 1-108] Top module 'netlist_wrapper_top.v' not found in any Verilog library

 

Finbarr

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2 Replies
Moderator
Moderator
478 Views
Registered: ‎07-21-2014

Re: Implementation - Vivado 2017.4 - merging 3'rd party EDIF netlists in a wrapper file.

@finbarrlong

 

I will need to look into the files to understand the issue, most of the time this issue happens because of stub file or incorrect edif generation.

 

I am moving this post to design entry board for further discussions.

 

Thanks

Anusheel

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Moderator
Moderator
437 Views
Registered: ‎06-14-2010

Re: Implementation - Vivado 2017.4 - merging 3'rd party EDIF netlists in a wrapper file.

Hello @finbarrlong,

 

Can you please try this in the GUI mode by creating a new post-syntheses design?

 

You can follow these steps to create a Post-synthesis project using the .v file and open the Synthesized design.
 

  1. Create a new Post-synthesis project.
     
  2. On the "Add Sources" page, click "Add Files..." and select the .v file.
     
  3. Go through the rest of the pages and manually select the target device.
     
  4. After the project is created, open the Synthesized design. 
    You will be prompted to specify the top level name. 
    Enter the top module name in the .v file (not the .v file name) and then the Synthesized design can be opened.

Can you give this a try and see if this will give you a better outcome?

If still failing as before, see if this will produce an additional info/message regarding the issue? If so, please share this with us for examination.

 

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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