04-09-2017 05:05 AM
I have generated the SEM core with the help of Xilinx documents (Soft Error Mitigation Controller v4.1 PG036). I can't find some objects mentioned in the document in my design. For example, FRAME_ECC primitive (page 88 ) or IO objects mentioned in page 90. I think these objects will appear after implementing the SEM core but I don't know how to instantiate the core in my design so that Vivado implement the core with my design.
04-09-2017 10:10 PM
04-10-2017 03:57 AM
I read these references and can open the example design, but I don't know how to integrate the SEM controller with my design (a simple counter). Now, the simple counter is placed and routed alone and I can't see the SEM controller after place and route in the device window. I know that after opening the IP (in a new instance of Vivado) it is possible to see their components. But there is the controller alone (without my design). Where should I instantiate the SEM core so that my design and the controller are placed and routed both?
A screenshot is attached from my project window.
top level: counter.v