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Newbie darren1982
Newbie
20,437 Views
Registered: ‎12-04-2012

Schematic Design Entry Tool in Vivado

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Hi,

 

I am learning how to use the new Vivado IDE and is trying to figure out how to create a schematic design in Vivado. I notice that we can do this in ISE using a schematic editor. 

 

But in Vivado, I couldn't specify a top level source type as schematic in when creating project and can't add a new source file of schematic type (sch file) to the project as well. There are only verilog or vhdl source type available. I can't find a similar schematic design entry tool in the Vivado IDE.

 

Does this means that I have to use the old ISE schematic edtior to create my schematic design and convert it to verilog before adding to my Vivado project? 

 

Thanks.

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1 Solution

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Xilinx Employee
Xilinx Employee
28,969 Views
Registered: ‎05-14-2008

Re: Schematic Design Entry Tool in Vivado

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Unfortunately, we don't have an equivalent tool like ISE Schematic Editor in Vivado.

 

Vivian

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18 Replies
Historian
Historian
20,421 Views
Registered: ‎02-25-2008

Re: Schematic Design Entry Tool in Vivado

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@darren1982 wrote:

Hi,

 

I am learning how to use the new Vivado IDE and is trying to figure out how to create a schematic design in Vivado. I notice that we can do this in ISE using a schematic editor. 

 

But in Vivado, I couldn't specify a top level source type as schematic in when creating project and can't add a new source file of schematic type (sch file) to the project as well. There are only verilog or vhdl source type available. I can't find a similar schematic design entry tool in the Vivado IDE.

 

Does this means that I have to use the old ISE schematic edtior to create my schematic design and convert it to verilog before adding to my Vivado project? 

 

Thanks.


This is the universe telling you to not use schematic entry for FPGA design.

----------------------------Yes, I do this for a living.
Newbie rpkh
Newbie
19,970 Views
Registered: ‎08-08-2013

Re: Schematic Design Entry Tool in Vivado

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@bassman59 wrote:

This is the universe telling you to not use schematic entry for FPGA design.


Why shouldn't we use schematic entry for FPGA design?

The IP Integrator in Vivado is kind of a schematic entry tool.
It only lacks some handy schematic entry features such as adding bus taps.



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Xilinx Employee
Xilinx Employee
28,970 Views
Registered: ‎05-14-2008

Re: Schematic Design Entry Tool in Vivado

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Unfortunately, we don't have an equivalent tool like ISE Schematic Editor in Vivado.

 

Vivian

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Teacher rcingham
Teacher
19,933 Views
Registered: ‎09-09-2010

Re: Schematic Design Entry Tool in Vivado

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> Why shouldn't we use schematic entry for FPGA design?

Because this is the 21st century.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Newbie 734
Newbie
19,552 Views
Registered: ‎12-14-2013

Re: Schematic Design Entry Tool in Vivado

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> Because this is the 21st century.

 

What? Why we can't use comfortable schematic design view as top level source type in the 21st century? Why did u do this!? It's very useful!

 

I'm frustrated :(

John Rambo disapproves this

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Newbie ermisp
Newbie
18,419 Views
Registered: ‎03-03-2014

Re: Schematic Design Entry Tool in Vivado

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You may not be able to design using schematics however you can visualise your design in a schematic view if you go to Flow Navigator -> RTL Analysis -> Elaborated Design -> Schematic. That way you are at least able to see what you design looks like...

Visitor stagger
Visitor
17,901 Views
Registered: ‎01-17-2008

Re: Schematic Design Entry Tool in Vivado

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Thanks a bunch for your helpful reply.

Given that you are rate as an "expert contributor" hereabouts, may I inquire about your field of expertise? Seems to me that you, and bassman59, are experts in the field of snarky replies to new users.

That does not seem to me to be the best way to build a user community.
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Visitor stagger
Visitor
17,897 Views
Registered: ‎01-17-2008

Re: Schematic Design Entry Tool in Vivado

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OK - I am "visualizing my design" in the schematic editor, after the insertion of an ILA via the debug "wizard" (talk about a term used loosely!)  The design compiled like a charm prior to giving it to the "wizard", but now it fails implementation, due to 3 open inputs on the ILA.  Via the schematic tool, I am able to "visualize" the nets I want to connect these open inputs to - they're part of a bus that flows right past the ILAs inputs, in fact - but I CAN'T make connection to them!  Can't do that in the HDL code I've written, either, because the ILAs aren't IN my HDL!

 

So, the value of this schematic tool is supposed to be what, exactly?  Increasing the frustration level of new Vivado users seems to be what it REALLY accomplishes.  It has shown me exactly what I want to do, and essentially dares me to get it done.

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Explorer
Explorer
15,947 Views
Registered: ‎09-02-2009

Re: Schematic Design Entry Tool in Vivado

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Using the ISE 14.7 when looking at the Schematic in the Implementation view

under the "Create Schematic Symbol"  there is "View HDL functional Model"

 

Click on it and it yields the .vhf file (or .vf in verilog)

Edit the file extension and change it to .vhd (or ,v for verilog)

 

Then you have the schematic VHDL or VERILOG file you can import in VIVADO

thanks everyone for the amazing help
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Visitor gmo
Visitor
6,044 Views
Registered: ‎07-01-2015

Re: Schematic Design Entry Tool in Vivado

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I also find it a petty that there is no more a schematic entry available in Vivado. We are developing, enhancing and maintaining a complex design now for over 10 years using different ISE versions. Specifically for the top level and some interim level I find schematics very useful, as they allow quick orientation between the different functional blocks, specifically when looking into the design again after a while. The methods found in Vivado to visualize the design with RTL Analysis do not help for primary navigation to the specific functional blocks and seem not to allow a manual optimized logical arrangement of the functional blocks. For sure a problem in ISE schematic entry is that “generate” methods available in e.g. VHDL to adapt the output of a project to some varying requirements could not be applied. But altogether it is difficult to move from ISE to Vivado because if the lacking schematic entry. Possible using a different front end tool like the ones available from ALDEC may allow to stay with schematic entry.

5,770 Views
Registered: ‎09-01-2015

Re: Schematic Design Entry Tool in Vivado

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I agree with gmo.. I have been working with Xilinx since their very first FPGAs.. 2064 IIRC.. about 30 years now..  I have used almost every different Xilinx device created.. I have always used Schematic capture.  In my current designs with 7c100t, the top level is schematic, lower levels are VHDL or schematic as is appropriate.  Perhaps some in FPGA design feel comfortable with VHDL because they are not used to hardware design represented by a schematic.

 

What I think is so interesting is that all the world is going drag-drop GUI pictorial like Simulink, but Xilinx is going backwards forcing programming!!  I can program VHDL with the best of them.. but sometimes a picture says a thousand words.

 

We need a schematic capture in Vivado.. Until then, I will use ISE to create VHDL for the areas I need a scematic.. Currently, I use ISE to ceate the VHDL for a 35T for Vivado.  Talk about clumsy.

 

Get with the program Xilinx..

Bryce

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Explorer
Explorer
5,539 Views
Registered: ‎09-02-2009

Re: Schematic Design Entry Tool in Vivado

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For the Drag and Drop one used ISE 4.2 because the Schematics and StateCAD (its including the wave simulation) are functionning

 

Then taking the resultant HDL and pluging it into Vivado does yield a good timing, probably due to the simplicity.

 

Now, the fact is those tools are removed so they must have had reasons for it, it could be that the IEEE 1076-2008 (VHDL)/ IEEE 1364-2001 (verilog) got too complex and the conversion from  the tools would not longer be sustainable, specially that uncertainties in the way the synthesis tools work also come into account and those synthesis tools are in software > 1Gbyte.  

 

There is the whole routing process that is not only not transparent but also not re-producable, not traceable, that is making the FPGA a hasard to the industry, its no wonder there is the emphasis on the DSP processing chips and they do have the predilection. 

 

The synthesis is clearly an issue but also the speed:

 

While trying yesterday 1billion ALU operations on a i5 standard processor 100$, in comparison to an artix7 33$ it seems that INTEL makes 302pS whereas XILINX 2500pS* at best from RAM to RAM (*measured and stable) through the ALU 

 

Hence this raises questions on why the Xilinx commercial presentation said: (http://www.xilinx.com/applications/megatrends/cloud-computing.html) "Through workload optimization, Xilinx can enable servers to deliver 10X the throughput" ?

 

It seems that the numbers do not add up

 

As long as synthesising wont allow the user code to "construct" and "deconstruct" functions in run time any comparison would only place the FPGA "slightly" ahead in the situation its actually cloning those cores with equivalent IPs that can run the same code, yet the price advantage is second to none there because the original providers are way ahead in optimising, and also for speed INTEL they run the RAM ALU cycle in 302pS?

 

On the other hand..

 

if there are 400 pins on an FPGA and one can slice the RAM in parallel elements in theory one would be able to run say 100 streams (for an instruction work lenght of 4 bits - that is far enough for to compete with the RISC) and provided one could have the logic elements "soft" switcheable partly, so after synthesis it would allow the code to modify the elements on demand, so in effect 100 ALU wouild "apprear" then one could have 12.5 pS per instruction/data cycle?

 

This feature for design tools is needed by industry,  for sure it is

 

For that reason the question is also raised how such concept if it would be made possible would have any chance of beeing taken into acocunt in the next design cycle?

 

Is there a channel where new concepts can be shown to Xilinx?

 

 

 

thanks everyone for the amazing help
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5,426 Views
Registered: ‎09-01-2015

Re: Schematic Design Entry Tool in Vivado

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It is not an issue that VHDL and Verilog is too complex. Schematic entry does not require a VDHL or Verilog design to be converted to a schematic. Rather, the schematic is converted to VHDL.  This conversion process only needs a subset of VHDL... Which already works.  The only thing the Schematic editor must do is create a wrapper for the VHDL, which already works.

 

For me, this issue is combining each design technology into a single design so I can use the strengths of Schematic entry, the strengths of VHDL and the strengths of Verilog as I deem necessary.  For instance some IP may be in VHDL, some in verilog.  However, the connection of these two technologies might be best visuallized by wiring the blocks together in a block diagram: Schematic.

Bryce

Observer joancab
Observer
5,078 Views
Registered: ‎05-11-2015

Re: Schematic Design Entry Tool in Vivado

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IP integrator allows to graphically connect IP blocks from library.

When one starts with programmable logic it seems natural to use schematics and basic blocks (gates, registers,etc.) but when your designs reach the 100s or 1000s of these elements, the logical move is into HDL languages and IPs. Vivado is probably designed for professionals and performance, so the schematic entry was dropped.

What is still possible (I guess) is to create your own IPs with your logic gates, FFs and basic blocks, then use IP integrator to wire them graphically. 

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Explorer
Explorer
4,961 Views
Registered: ‎09-02-2009

Re: Schematic Design Entry Tool in Vivado

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Important note for those wanting to use the block designs (Vivado) the same as  schematics where used (ISE) there is the need to create LOGIC gates libraries. To build libraries in Vivado to create the Block Editors use

 

  • XUP_LIB.zip in attachment and the
  • xup_building_basic_elements_lab.pdf tutorial

so you can build the library of gates and mingle with them for the schematics in Vivado (Block Design Editor)

 

Good Luck 

thanks everyone for the amazing help
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Visitor prof.glauco
Visitor
2,304 Views
Registered: ‎06-20-2018

Re: Schematic Design Entry Tool in Vivado

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This is an absurd!! 

That´s why I postpone the use of Vivado and try to keep on ISE and Quartus. 

Now probably I will install an older version of ISE to draw an schematic and import to Vivado. I have to do the work that Xilinx dont want to do.

 

How can I teach the basics of a digital counter without a schematic?  This is not electronics, now it is only C language programming.

 

How can a so powerful tool not present a schematic editor and a VHDL converter??

 

 

It´s like to take out the "start" button on windows....

Visitor prof.glauco
Visitor
2,304 Views
Registered: ‎06-20-2018

Re: Schematic Design Entry Tool in Vivado

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I will take this is as a sarcastic response.
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Adventurer
Adventurer
320 Views
Registered: ‎05-16-2014

Re: Schematic Design Entry Tool in Vivado

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Altera's Quartus has schematic entry. That is all they use at Fermi National Accelerator Laboratory. If accelerating protons to the speed of light isn't 21st Century I don't know what is!

Also, there are plenty of legacy designs that used schematic entry and are being converted to RTL code. But one has to understand schematic entry to work with.

Block diagram is a little higher level than schematic entry. 

You could always use the schematic view funtion from the netlist.

My gut feeling is that Xilinx figured there wasn't enough people doing schematic entry. So why support it. Can't blame them.

I've done schematic entry. Interesting, right down to the bit level.  But I prefer VHDL code. Block diagrams are nice for Zynq processors or microblaze processors.

 

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