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Visitor ricardosrl
Visitor
2,345 Views
Registered: ‎03-30-2017

Set module pin value on sdk

Greetings

 

I have a vivado project generated through the git repository of analog devices for the PicoZed SDR. After I compiled the project, I exported into sdk and added the files also made available by analog devices related of no-OS, I was able to transmit a sinusoid at a given frequency.

 

Now I wanted to take the next step in my project and pass samples of a chain that I coded myself using VHDL. But I did not want to lose the functionality of transmitting the sinusoid that the system already transmits. So I created a module that serves as a multiplexer (Figure below) with a select bit to switch between the two sample sources.

 

Samples Mux

 

What I intended to do would be to access the select through the SDK so I can configure it as I configure the rest of the system. At this point I can change frequency of transmission, reception, gains, etc. through a terminal connected to the uart (all this is made available by no-OS, I just put together the reference design of the card with no-OS). I've done some research, but I'm not sure what I'm looking for either. I'm still very new to FPGAs, especially to SDK. If someone could point me in the rigth direction I would be very grateful. I think I have to associate the select bit to a register and then access it in the SDK, but I do not know how to do that.

 

Relevant links:
Reference design of PicoZed SDR in git - https://github.com/analogdevicesinc/hdl
No-OS in git - https://github.com/analogdevicesinc/no-OS


Thank you for you're time.

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Moderator
Moderator
2,294 Views
Registered: ‎11-09-2015

Re: Set module pin value on sdk

Hi @ricardosrl,

 

As how your IP is made (external sel pin), I would suggest to use an AXI GPIO IP connected to the picozed. The you can use the AXI interface to change the values of the GPIOs output so the value of the sel pin.

 

Another suggestion would be to create an AXI interface in the IP to have registers accessible from the pricozed (the the sel pin would not be external but a register bit inside the IP).

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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