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Registered: ‎03-16-2012

Super sample rate support for RTL / block design IP catalog



Support has recently been announced by Xilinx for Super Sample Rate blocks in System Generator 2018.3. These blocks (including FFTs and FIR filters) are designed to handle multiple parallel samples per clock sample.


As far as I can tell, this support does not extend to the Vivado 2018.3 / 2019.1 RTL IP catalog or the Block Designer IP catalog.


1) Are there any plans by Xilinx to add Super Sample Rate support to the Vivado RTL IP / Block Design IP catalog of components (such as FFTs and FIR compilers)?

2) I am specifically looking for an 512 point FFT that can process N samples per clock cycle (currently N is 4 but this would need to increase in future revisions). Does anyone in the community have any recommendations for an HDL parallel FFT core that has been tested and is known to work reliably?


Thank you.



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