SystemVerilog import VHDL package error

[marver]

Hello,

I have a SystemVerilog (.sv) testbench that instantiates VHDL (.vhd) design files. In the testbench, I need to use a record defintion from a VHDL package file. When I try to import pkg::*; in the .sv testbench, Vivado gives an error during compilation:

xvlog -m64 --relax -prj sw_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "tb.sv" into library xil_defaultlib
ERROR: [VRFC 10-91] pkg is not declared [tb.sv:3]

I changed the compile order in the Vivado window so the pkg.vhd file is compiled before tb.sv, however this error still persists. I've also tried `including the .vhd package file instead of importing, however that generates a syntax error as they are different language files.

Any ideas?

[vijayak]

Hi @marver

Can you please post simple code that demonstrates your usage for better understanding?

[marver]

Hi @vijayak,

  Here's a snippet of tb.sv

`timescale 1ps/100fs

import pkg::*;

module tb;
  local_bus_record sys_ctrl_bus;
  //...
endmodule

and here's a snippet of the pkg.vhd file

library ieee;
use ieee.std_logic_1164.all;

package pkg is
  type local_bus_record is record
    reg_ack  : std_logic;
    reg_data : std_logic_vector(31 downto 0);
  end record local_bus_record;
end;

[vijayak]

Hi @marver

I am able to reproduce the issue with Vivado and seeing the same issue with Questa as well.

I will get back to you soon on this.

[hweng]

What was the solution/outcome here? I'm having an identical issue in 2016.2

[oft]

Hi

Is there a solution to that problem yet?

and in general - how well xilinx tools work both with VHDL and Verilog/SystemVerilog files?

oft