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Participant
Participant
12,251 Views
Registered: ‎10-05-2015

The design (.edf file) in custom packged IP cannot be found in synthesis

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Hi all,

   I packaged an IP with the design in a .edf file. In tool "create and package IP", there is no warning or error reported. However, when I used this packaged IP in IP integrator to construct another system, the systhesis reported the packaged module cannot be found. I tried to use the design in .v file, the synthesis is OK. So what is the correct steps to add an IP with the design in edf file? Thanks much.

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Participant
Participant
20,511 Views
Registered: ‎10-05-2015

The problem can be solved after setting .edf file as the synthesis source. Thanks much.

View solution in original post

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Moderator
Moderator
12,238 Views
Registered: ‎07-01-2015

Hi @zhengyudennis1,

 

Please write the complete error message you are getting and steps to reproduce your issue.

 

Thanks,
Arpan

Thanks,
Arpan
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Xilinx Employee
Xilinx Employee
12,222 Views
Registered: ‎09-20-2012

Hi @zhengyudennis1

 

Is the EDIF file complete or do you have seperate EDIF files for sub-modules? 

 

In the block design if you right click on the IP and select "edit in ip packager", do you see the EDIF file in the file groups section of IP packager project?

 

Which version of Vivado are you using?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Participant
Participant
12,208 Views
Registered: ‎10-05-2015

The error message is [Synth 8-439] module '*****' not found.

When I go back to the IP packager, I want to add the EDIF file again. The follows error shows:

ERROR: [Vivado 12-3630] The destination file '******.edf' already exists, please use -force if you want to overwrite! 

It means that the edf file has been added into. However, I cannot find it in the "Design Sources".

I tried to use an empty .v wrapper to wrap the edf file, an empty module is synthesized out.

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Participant
Participant
12,205 Views
Registered: ‎10-05-2015

EDIF file is a block design (no submodule edf file) that is planed to integrate into another system. I added it in "add source file", but I did not see it in file group selection. If I re-added it, an error shows that it is already there. The Vivado version is 2015.3.

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Xilinx Employee
Xilinx Employee
12,184 Views
Registered: ‎09-20-2012

Hi @zhengyudennis1

 

Can you attach a snapshot showing the "file groups" section of IP packager project?

 

Do you see any warnings/critical warnings when you package the IP?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
12,179 Views
Registered: ‎06-24-2015
Hi @zhengyudennis1,

Try the following steps and see if they help:
1) Open Block design
2) Right Click on Custom IP block {Indicated in error message}
3) Click on Edit in IP packager
4)Go to IP files group --> Is Include ( Unchecked this column)
5)Go to Review and Package --> Re-package IP
6) Then Validate the complete block design and Re-run the synthesis

Thanks,
Nupur
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Accept as solution if it resolved your query, give kudos(star on left) if it led you to the solution.
Thanks,
Nupur
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Participant
Participant
12,173 Views
Registered: ‎10-05-2015

Hi,

  There was no warning. Everything went normally.

  After exploratioin, I found that Vivado ignores the .edf file as synthesis source by default (this is very strange). You must set it as synthesis resource by yourself in IP packager. Hope it can save other people's time. 

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Participant
Participant
20,512 Views
Registered: ‎10-05-2015

The problem can be solved after setting .edf file as the synthesis source. Thanks much.

View solution in original post

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