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Explorer
Explorer
155 Views
Registered: ‎12-05-2016

UART data is getting currepted when RX line is reconnected

 

Hi all,

I am trying to do a custom UART - RX module in VHDL. I am able to receive the data sent from PC.

But my problem is when RX wire is disconnected and re-connected my data will be erroneous

In my current logic, I didnt add any error control mechanism. What could be the possible ways of doing the same? 

How can I detect that my cable is reconnected so that I can set my FSM to a default or reset state? FSM is attached in the image. 

Thanks & Regards,

Reshma 

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uart_rx_fsm.JPG
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6 Replies
127 Views
Registered: ‎01-22-2015

Re: UART data is getting currepted when RX line is reconnected

Reshma,

-try using a timeout timer.  That is, write a VHDL process that, when triggered, will count down from some constant value to zero and then raise a time-out flag.

Then, in the VHDL process that implements your FSM, the IDLE state should trigger the timeout timer when a start bit is detected on the RX wire. If the IDLE state does not detect the start bit then it turns off the timeout timer.  Also in this VHDL process, write new code that checks the timeout flag before allowing control to enter the FSM. If the new code finds that the timeout flag is set, then it clears the flag and tells the FSM to return to the IDLE state.

Mark

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Explorer
Explorer
102 Views
Registered: ‎12-05-2016

Re: UART data is getting currepted when RX line is reconnected

 

Hi markg@prosensing.com ,

Thanks for your reply. 

But I didnt get it properly. I will describe the logic to be implemented as per your suggestion. Please correct me if I am wrong.

  • A timer will be running - which triggers when a start bit is detected on RXD
  • New control logic for FSM - Checks control flag before allowing control to FSM. If flag is set, it will be cleared and FSM will return to IDLE state.  -  This section is not clear to me

Could you please give more clarity?

Thnaks & Regards,

Reshma  

 

 

 

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Scholar dgisselq
Scholar
92 Views
Registered: ‎05-21-2015

Re: UART data is getting currepted when RX line is reconnected

@reshmaakhil,

UART doesn't really have any good error control mechanisms.  That said, there are two things you might consider using:

  1. The UART protocol includes a "break condition" defined by the serial port being held low (0) for an extended period of time.  I can never remember exactly how long this is, but it is certainly longer than a typical byte transmission.  If you disconnect your serial port, the wire should go low like this.  You should be able to detect the problem on entry (a start bit with no corresponding stop bit 8-bits later), but this doesn't help so much when plugging the cable in later and the line "bouncees".
  2. The serial protocol also offers "parity".  You might be able to implement either odd or even parity to help reject some of this noise.  In practice, however, you'll find that most serial ports just suck up the noise and report bad data rather than using the parity bit.

After those two, if you are still having problems, then you may need to get fancy.

  1. You could check/verify that the serial port "bits" don't change mid-baud,  and if they do reject any bytes received
  2. You could check that you only receive whole (or nearly whole) stop bits--or even two-stop bit periods in a row if using an extra stop bit.

These last two only sort of match the serial protocol, but they might match good enough for you to be successful trying them.

Just my thoughts,

Dan

Highlighted
82 Views
Registered: ‎01-22-2015

Re: UART data is getting currepted when RX line is reconnected

@reshmaakhil 

The VHDL snippets below shows key concepts of the timeout timer approach.  Note how run_timer is used to start and stop the timeout timer and to clear the flag, timeout.

type state_type1 is (IDLE,s_RX_START,s_RX_Data,....);
signal my_state : state_type1;
signal CLK, RST, run_timer, timeout : std_logic;
--        
P1: process(CLK)                      --timeout timer
constant CNTRMAX : integer := 10000;
variable cntr  : integer range 0 to CNTRMAX;	          
begin 
    if rising_edge(CLK) then        
        if(run_timer = '0') then         
            cntr := CNTRMAX;
            timeout <= '0';         
        else  
            if(cntr = 0) then     
                timeout <= '1'; 
            else      
                cntr := cntr - 1;
                timeout <= '0';                               
            end if;
        end if;
    end if;    	
end process P1;

P2: process(RST,CLK)                 --Reshma FSM
begin        
    if rising_edge(CLK) then  
        if ((RST = '1') or (timeout = '1')) then                        
            run_timer <= '0';                                                                   
            my_state <= IDLE;     
        else
            case my_state is                    
                when IDLE =>  
                    if (start_bit = '1') then   --start bit detected?
                        run_timer <= '1'; 
                        my_state <= s_RX_START; 
                    else                    
                        run_timer <= '0'; 
                        my_state <= IDLE;
                    end if;
                    
                when s_RX_START =>
                ...
                when s_RX_Data =>
                ...
            end case;
        end if;     
    end if;        
end process P2;

 

 

 

Explorer
Explorer
72 Views
Registered: ‎12-05-2016

Re: UART data is getting currepted when RX line is reconnected

 

Hi,

@dgisselq ,

Thanks for the inputs. 

I will check these points.

Regards,

Reshma 

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Explorer
Explorer
66 Views
Registered: ‎12-05-2016

Re: UART data is getting currepted when RX line is reconnected

 

Hi markg@prosensing.com ,

Thanks for your kind support.

I missed the point.

            if ((RST = '1') or (timeout = '1')) then
                run_timer <= '0';
               my_state <= IDLE;

Now the logic is almost clear. I will try to implement the same & update the results .

Regards,

Reshma

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