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7,668 Views
Registered: ‎07-26-2013

Unable to add xci file of async fifo to project

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Hello,

  I am trying to add the .xci file of async fifo core to my RTL project using below command

add_files -norecurse fxt_async_fifo/project_1.srcs/sources_1/ip/async_fifo_core/async_fifo_core.xci

 

While doing so the tool doesnt add the xci file giving the below message.


CRITICAL WARNING: [Designutils 20-1381] The sub-design source file can not be added to the current project since there is an overlap between the sub-design directory structure and the project directory structure. Sources representing Embedded/DSP/IP sub-designs need to be located in their own directory structure. Allowing the project directory structure to overlap with the sub-design directory structure will cause errors later in the flows for any operation that requires the sub-design to be local to the project. Examples of these operations are: copying the sub-design to the project locally, project archive, project save as etc.

 

I have never seen this kind of issue ever before.

If in my RTL project , i open the IP catalogue and create the async_fifo, it gets added to the project.

But if the async_fifo xci is generated outside the project using Manage IP or even seperate rtl project, that xci file is not accepted by this project.

 

The reason for solving this, is i want to later create a script based project so that all ip cores should be simply added using add_files -norecourse command.

Dont wish to locally generate any IP everytime a new project is created.

 

-Sachin

 

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Highlighted
11,616 Views
Registered: ‎07-26-2013

Hi Deepika,

 Well i found the solution. Basically we should not keep the ip directory in the same directory as the project directory.

The IPs should be placed OUTSIDE the project directory.

 

 

The issue doesnt come that way.

 

 -Sachin

View solution in original post

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4 Replies
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Xilinx Employee
Xilinx Employee
7,663 Views
Registered: ‎09-20-2012

Hi,

 

Can you try copying the .XCI file to a different location and try to add it?

 

Check if this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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7,658 Views
Registered: ‎07-26-2013

Hi Deepika,

  I have done that many times yesterday. The only way the axi is added,if the ip is locally generated in the project.

You can try that at your end.

1)Create a fifo using manage ip.

2)Then create a rtl project with fifo wrapper file.

3)Try adding the fifo created using manage ip.

 

you will get the same error.

 

Sachin

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Xilinx Employee
Xilinx Employee
7,645 Views
Registered: ‎09-20-2012

Hi Sachin,

 

I have tried to follow the process you mentioned. Created a IP using "Manage IP" at a remote location.

 

Added this IP file to a new project created at a different location. I did not get the warning you mentioned. I have used vivado 2013.2.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Highlighted
11,617 Views
Registered: ‎07-26-2013

Hi Deepika,

 Well i found the solution. Basically we should not keep the ip directory in the same directory as the project directory.

The IPs should be placed OUTSIDE the project directory.

 

 

The issue doesnt come that way.

 

 -Sachin

View solution in original post

0 Kudos