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Newbie corwin
Newbie
3,575 Views
Registered: ‎03-17-2010

Unable to assign pins on my XC9500XL design

I'm a newbie to ISE and am using v 11.5. My design is a simple one in a XC9536XL part. I have completely entered the design in the schematic editor and everything fits, but I cannot get the pins to assign. The Pace tool consistantly complains with many errors like:

 

ERROR:DesignEntry - Could not apply constraint: NET "RES_OUT"  LOC = "P14"  ;

 

It fails every i/o net in my design. I've tried running PACE specifying the .NGD file for my design, and I get no complaints about my nets, but it also doesn't seem to do anything. At the end of the process, the design is assigning pins at will and many of my signals are not routed to pins at all.

 

I've deleted the 'ucf' file and generated a new one, with no success. This all seems so basic, yet after hours of fiddling, I am failing.

Help.

 

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Xilinx Employee
Xilinx Employee
3,561 Views
Registered: ‎12-17-2007

Re: Unable to assign pins on my XC9500XL design

Corwin,

 

This is a known problem with our CPLD designs and the floorplanner tool if your top-level is a schematic.  If this is the case for you, check out AR 22268 (http://www.xilinx.com/support/answers/22268.htm).

 

-Tony 

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