UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mdeepakm
Visitor
175 Views
Registered: ‎09-30-2019

Unable to export hardware from Vivado 2018.3 to SDK

Jump to solution

Hello,

   I created an AXI-4 master and slave streaming IP. Connected it to Zynq IP and AXI - DMA using a block diagram. I managed to generate the bitstream file. But I am unable to export the hardware. On trying to export hardware, I am getting the following error: "Cannot write hardware definition file as there are no generated IPI blocks". I want to launch SDK and write driver C code. Please let me know how to solve this issue. I have attached the archive.

Regards

Tags (1)
1 Solution

Accepted Solutions
Moderator
Moderator
125 Views
Registered: ‎03-25-2019

Re: Unable to export hardware from Vivado 2018.3 to SDK

Jump to solution

Hi @mdeepakm,

Please create HDL wrapper and Generate the Output Products for your design before trying to export the HDF file:

wrapper.png

output.png

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

3 Replies
Moderator
Moderator
126 Views
Registered: ‎03-25-2019

Re: Unable to export hardware from Vivado 2018.3 to SDK

Jump to solution

Hi @mdeepakm,

Please create HDL wrapper and Generate the Output Products for your design before trying to export the HDF file:

wrapper.png

output.png

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution

View solution in original post

Visitor mdeepakm
Visitor
97 Views
Registered: ‎09-30-2019

Re: Unable to export hardware from Vivado 2018.3 to SDK

Jump to solution

Hello,

    Thanks a lot for the reply. That helped. But now I face a different issue. On trying to export the hardware with bitstream, I get the following message:

The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export. 2. There are no block design hardware handoff files. Check the vivado log messages for more details

Capture1.PNG

 

To solve it, I tried the TCL commands given here

write_hwdef -force -file C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/synth_1/design_1.hwdef

write_sysdef -force -hwdef C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/synth_1/design_1.hwdef -bitfile ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.bit -file C:/Users/deepa/ip_repo/edit_test2_v1_0.runs/impl_1/design_1.sysdef

But looks like no HWDEF file is created. 

Regards

 

 

 

 

 

 

 

0 Kudos
Visitor mdeepakm
Visitor
75 Views
Registered: ‎09-30-2019

Re: Unable to export hardware from Vivado 2018.3 to SDK

Jump to solution

Hi,

    I created the project in the Xilinx installation folder and set the design_1 wrapper.v file as top and then generated the bitstream. After this step, I am able to export it to SDK.

 

Regards

0 Kudos