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Visitor
Visitor
6,611 Views
Registered: ‎12-08-2016

Update IP does not change implemented design

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Hello,

 

I am working on a design where I have several of my own IP cores packaged and placed into a block diagram.  If I make a change to the IP core, either by right clicking on the IP and choosing "Edit in IP Packager" (for HDL only IP) or by opening the project (Block Diagram based IP), then repackage the IP, I am notified when returning to the top level diagram that the IP has changed and must be updated.  

 

After running the IP status report and updating IP, I am prompted to re-generate the output products.  I then re-generate the output products and run synthesis, implementation, etc.  Upon loading the new bitstream, the design changes are not present in the hardware.  I have verified this several ways: hardware IO, ILAs, and reviewing the synthesized schematic.

 

However, if I run the report, update, and reset the output products before re-generating them, everything works as it should.  While it does work, it is slow and seems to negate the benefits of OOC builds, as resetting the output products causes each IP to re-synthesize.

 

My question is whether or not this is the proper procedure for re-synthesis after IP upgrade.  It seems as though simply running the upgrade and re-generating the output products should be sufficient, but without the reset it does not work.

 

Thanks,

 

Jeff

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Visitor
Visitor
10,356 Views
Registered: ‎12-08-2016

After some experimentation and attempts to narrow down what exactly caused the error, it seems as though the missing step was generation of output products in the IP block diagram.  We haven't tested this very thoroughly, but the problem seems to be resolved.

View solution in original post

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Xilinx Employee
Xilinx Employee
6,564 Views
Registered: ‎10-24-2013

Hi @jlimbocker

Is this behavior seen with the latest version of Vivado 2016.3?

If not, please try using the latest version.

Thanks,Vijay
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Moderator
Moderator
6,552 Views
Registered: ‎01-16-2013

Hi,

 

Below are the steps you need to perform for edit and update IP.

click IP catelog

right click IP -> edit in IP packager

click OK ... takes a few seconds to create a new subproject

click OK to overwrite previous version of the subproject created by my previous edit

double click the HDL source file and navigate to where I want to make the change

save the file

click "package IP tab"

click "review and package"

click "Re-package IP" button

subproject disappears

 

Apart from this there is no required/extra step for this flow.

 

Can you please tell if you follow the steps mention above, you face issue or not?

 

Thanks,
Yash

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Explorer
Explorer
6,533 Views
Registered: ‎11-25-2015

@jlimbocker

 

You only need to upgrade ip and re-generate output products once you re-package the IP.

Is your report_ip_status showing latest versions being used? Can you list the steps you are following?

 

Regards,

Sravanthi

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Visitor
Visitor
6,517 Views
Registered: ‎12-08-2016

I have observed this with both 2016.2 and 2016.3.  

 

There are two procedures I have to follow depending on the way the IP was created.  The first is with regards to IP that do not contain a block diagram, the second is used when the IP is based off of a block design.  This is because the block design does not get packaged into the IP and is not reopened when the IP is edited from the project rather than the IP Packager.  The methods are outlined below:

 

Method 1 (HDL only IP):

 

  1. Open IP catalog
  2. Locate IP to be edited
  3. Right click and select "Edit in IP Packager"
  4. Allow creation of temporary project
  5. IP Packager opens
  6. Make changes
  7. Click "Package IP" in the flow navigator
  8. Review changes
  9. Click "Re-Package IP"
  10. Project Closes

Method 2 (Block Diagram based IP):

 

  1. Open project from which IP was created
  2. Make changes
  3. Click "Package IP" in the flow navigator
  4. Review changes
  5. Click "Re-Package IP"
  6. Close Project

 

At this point, I am prompted that the IP catalog has been changed, so I click on the message in the ribbon to run the IP Status report.  This report indicates that the IP versions in the project are behind those in the repository.  I click upgrade, the IP is upgraded, and I am prompted to generate the output products.  After generation, I synthesize, implement, and generate bitstream.  After loading the bitstream, the changes are not reflected in hardware.  The changes are also not reflected in the schematic.

 

It is worth noting that when following the exact same procedure with the addition of resetting output products before generation, everything works as it should.  It also works to delete the old block from the block design and add the updated version to the block diagram.

 

I am working on a project that demonstrates the issues I am having and can provide the TCL commands generated by vivado to illustrate the process if it helps.

 

Jeff

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Explorer
Explorer
6,493 Views
Registered: ‎11-25-2015

@jlimbocker

 

Your flow seems to be fine. Can you share the project archive with TCL script to reproduce the issue?

 

Regards,

Sravanthi

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Visitor
Visitor
10,357 Views
Registered: ‎12-08-2016

After some experimentation and attempts to narrow down what exactly caused the error, it seems as though the missing step was generation of output products in the IP block diagram.  We haven't tested this very thoroughly, but the problem seems to be resolved.

View solution in original post

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Xilinx Employee
Xilinx Employee
6,423 Views
Registered: ‎10-24-2013

Hi @jlimbocker

Thanks for posting the solution. Please mark the solution in the interest of other users.

 

Thanks,Vijay
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Highlighted
3,190 Views
Registered: ‎05-22-2017

I have tried the proposed solution but continue to have problems with getting the implemented design to update.

 

The steps are as follows:

1. In the Project Manager tab, in IP Sources window select the xci file for the IP to be edited and right click.

2. Select Edit in IP packager,

3. A pop up dialog then asks you to choose a project name and location for editing and I make no changes and click the OK button. (see attached image Edit in IP Packager.png).

4. Confirm Overwrite, click OK.

5. In the Project Manager tab, select the IP source file to edit

6. Make changes and save the file

7. Open the Package IP tab and review the changes merge data as needed.

8. Click on Re-Package IP

9. Pop up dialog called Close Project click on Yes.

10. in the main project instance of vivado view the IP Status, (this is found in Tools->Report->Report_IP_Status

11. Select the IP that has just been edited and click Upgrade Selected. 

12. the Generate Output Products dialog pops up see attached file "Generate Output Products.pgn. 

13. Click Generate and wait for that to complete, a dialog box pops up called Generation of output products completed successfully.

14. Now at this point I would expect the changes I have made in the IP Packager should have been copied across to the IP source files in the project, but they aren't.

 

Using file search in windows to look for the IP source file in the project folder I find two copies in seperate folders:

 

The first one is the file that has just been edited in the packager and the second is the file that exists in the project.

C:\MZ\RubyTH2\RubyTH2.srcs\sources_1\bd\mz\rubyth2\ip_repo\edit_TDCtest_v1_0.srcs\sources_1\new\TDC_test.v

 

C:\MZ\RubyTH2\ip_repo\edit_TDCtest_v1_0.srcs\sources_1\new\TDC_test.v

 

The problem is that the second file has not been updated.

 

Is it because there is an error in the edited file?  If so which log file should I look in to find what the error is?

Alternatively am I following the wrong steps?

 

 

 

 

 

 

 

 

  1. Make changes
  2. Click "Package IP" in the flow navigator
  3. Review changes
  4. Click "Re-Package IP"
  5. Close Project
Edit in IP Packager.png
Generate Output Products.PNG
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Moderator
Moderator
3,176 Views
Registered: ‎11-09-2015

Hi john.potter@redsensors.co.uk,

 

Our Community Help has a tip that might help you : Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

 

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

I would suggest you create a new topic on the appropriate board

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Highlighted
2,291 Views
Registered: ‎05-22-2017
OK will do
Thanks
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