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Registered: ‎01-16-2020

Upgrading IP blocks makes my Vivado 2018.2 project fail

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Hi,

I am beginner with Xilinx software. I am basically trying to increase the frequency of the IP block 'clock wizard 6.0' (clk_wiz_0 in the image) of an existing project created by another person. I thought it was going to be as simple as double clicking on the block and changing the 'Requested frequency' of the output clock. However, to do so, Vivado must upgrade 4 of the blocks first. I don't understand why I need to upgrade the IP blocks when the Vivado version used is the same as before. The current version and the recommended version of the blocks is also the same.

If I do not upgrade IP, my project works fine. I can run synthesis, implementation, generate bitstream, export to SDK and program the FPGA just fine. I know it works because I can probe the outputs 'register_outputs0[31:0]' of the Diagram through a MicroZed Breakout Carrier Card for my MicroZed FPGA (xc7c010clg400-1, ps7_cortexa9_[0-1]). However, as soon as I upgrade the IP blocks and go through the same flow I do not see anything in any of the outputs anymore. Why could this be? Please, some help for a desperate newbie, :)

UpgradeIP.jpg

 

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Voyager
Voyager
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Registered: ‎06-28-2018

Hi alejandro.diaztormo@ugent.be 

The reason for the IP upgrade for Xilinx IPs is shown as 'IP board change'. Please make sure you're targeting the correct board/part. I would try removing and reinserting ZYNQ7 Processing System and run block automation after confirming that the target device is correct.

Also the user IP has had a lot of version changes, the latest revision might have some problems. You can skip upgrading this IP and see if anything changes.

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Voyager
Voyager
396 Views
Registered: ‎06-28-2018

Hi alejandro.diaztormo@ugent.be 

The reason for the IP upgrade for Xilinx IPs is shown as 'IP board change'. Please make sure you're targeting the correct board/part. I would try removing and reinserting ZYNQ7 Processing System and run block automation after confirming that the target device is correct.

Also the user IP has had a lot of version changes, the latest revision might have some problems. You can skip upgrading this IP and see if anything changes.

View solution in original post

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325 Views
Registered: ‎01-16-2020

Thanks to your comment I checked more thoroughly the message I get when clicking on the 'IP board change' label. It says that the current project board 'unset' and the board 'em.avnet.com:microzed_7010:part0:1.1' do not match. That made me look into how to import the corresponding Board Definition Files into Vivado and voila', it works! I simply did not have those files.

In case it helps somebody else, you can solve the issue by:

1 - download the corresponding Board Definition Files from the board website, in my case http://zedboard.org/support/documentation/1519

2 - copy the folder corresponding to my board (microzed_7010/1.1 in my case) into the Vivado board_files folder: ...Xilinx\Vivado\2018.2\data\boards\board_files.

3 - Restart Vivado. It should automatically detect and link the IP blocks, so it should not tell you that you need to update the IP of those blocks anymore. If not, try updating the targeted device under settings/project device.

Thanks @baltintop!