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Explorer
Explorer
7,959 Views
Registered: ‎11-13-2009

Using Verilog Attribute KEEP to force known address bus width

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My design relies on a common custom Dual Ported Memory block, which has the RAMB36E1 instanciated in CASCADE mode. Often this block has one port tied to a Microblaze based design by Externalizing the BRAM_Controller Port and the second port is tied somplace in the hardware.

 

The hardware may use this memory interface sequencially for data patterns or randomly if we are using it as a coefficent mailbox.

 

The problem that I just uncovered is that the default V7 Memory Primitive behavior is to tied unused addresses HIGH.  Not a problem for the Microblaze Port, but for the hardware port the address size may be changing based on usage for the hardware side.

 

So I wanted to know if declaring the "reg" that attached to the hardware port with a KEEP makes sense.  So I have something like:

 

   (* keep = "true" *) reg [15:0]           ZeroRamAddress, OneRamAddress;

 

Will this ensure that all 16-bits of my address are kept around and wired all the way through implementation?  Is there a better way to do this with what really ends up being a re-used block?

 

TomT...

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Explorer
Explorer
13,965 Views
Registered: ‎11-13-2009

Re: Using Verilog Attribute KEEP to force known address bus width

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Well after a few hours run and some chipscopes I have my answer.  Yes this works as expected.

 

Thanks all who viewed,

TomT...

View solution in original post

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Explorer
Explorer
13,966 Views
Registered: ‎11-13-2009

Re: Using Verilog Attribute KEEP to force known address bus width

Jump to solution

Well after a few hours run and some chipscopes I have my answer.  Yes this works as expected.

 

Thanks all who viewed,

TomT...

View solution in original post

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