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Scholar ronnywebers
Scholar
9,745 Views
Registered: ‎10-10-2014

Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello,

 

I discovered several unexpected warnings in Vivado when making a basic design with the Zedboard :

 

just doing these basic steps :

 

1) create new project, select Zedboard

2) add Zynq

3) run block automation & connection automation

4) connect FCLK_CLK0 to M_AXI_GP0_ACLK

5) create wrapper

6) generate bitstream

 

In 2014.4 this worked just fine, howver in 2015.3 :

 

I get 3 sysnthesis warnings :

 

[Synth 8-992] S_AXI_GP0_ACLK_temp is already implicitly declared earlier ["i:/Repositories/Zynq/2015_3/LwIP/LwIP.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v":2701]

 

[Synth 8-992] S_AXI_GP1_ACLK_temp is already implicitly declared earlier ["i:/Repositories/Zynq/2015_3/LwIP/LwIP.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v":2702]

 

[Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given ["i:/Repositories/Zynq/2015_3/LwIP/LwIP.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v":316]

 

A placement warning :

 

[Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are:
FIXED_IO_mio[53] of IOStandard LVCMOS18
FIXED_IO_mio[52] of IOStandard LVCMOS18
FIXED_IO_mio[51] of IOStandard LVCMOS18
FIXED_IO_mio[50] of IOStandard LVCMOS18
FIXED_IO_mio[49] of IOStandard LVCMOS18
FIXED_IO_mio[48] of IOStandard LVCMOS18
FIXED_IO_mio[47] of IOStandard LVCMOS18
FIXED_IO_mio[46] of IOStandard LVCMOS18
FIXED_IO_mio[45] of IOStandard LVCMOS18
FIXED_IO_mio[44] of IOStandard LVCMOS18
FIXED_IO_mio[43] of IOStandard LVCMOS18
FIXED_IO_mio[42] of IOStandard LVCMOS18
FIXED_IO_mio[41] of IOStandard LVCMOS18
FIXED_IO_mio[40] of IOStandard LVCMOS18
FIXED_IO_mio[39] of IOStandard LVCMOS18
FIXED_IO_mio[38] of IOStandard LVCMOS18
FIXED_IO_mio[37] of IOStandard LVCMOS18
FIXED_IO_mio[36] of IOStandard LVCMOS18
FIXED_IO_mio[35] of IOStandard LVCMOS18
FIXED_IO_mio[34] of IOStandard LVCMOS18
FIXED_IO_mio[33] of IOStandard LVCMOS18
FIXED_IO_mio[32] of IOStandard LVCMOS18
FIXED_IO_mio[31] of IOStandard LVCMOS18
FIXED_IO_mio[30] of IOStandard LVCMOS18
FIXED_IO_mio[29] of IOStandard LVCMOS18
FIXED_IO_mio[28] of IOStandard LVCMOS18
FIXED_IO_mio[27] of IOStandard LVCMOS18
FIXED_IO_mio[26] of IOStandard LVCMOS18
FIXED_IO_mio[25] of IOStandard LVCMOS18
FIXED_IO_mio[24] of IOStandard LVCMOS18
FIXED_IO_mio[23] of IOStandard LVCMOS18
FIXED_IO_mio[22] of IOStandard LVCMOS18
FIXED_IO_mio[21] of IOStandard LVCMOS18
FIXED_IO_mio[20] of IOStandard LVCMOS18
FIXED_IO_mio[19] of IOStandard LVCMOS18
FIXED_IO_mio[18] of IOStandard LVCMOS18
FIXED_IO_mio[17] of IOStandard LVCMOS18
FIXED_IO_mio[16] of IOStandard LVCMOS18
FIXED_IO_mio[15] of IOStandard LVCMOS33
FIXED_IO_mio[14] of IOStandard LVCMOS33
FIXED_IO_mio[13] of IOStandard LVCMOS33
FIXED_IO_mio[12] of IOStandard LVCMOS33
FIXED_IO_mio[11] of IOStandard LVCMOS33
FIXED_IO_mio[10] of IOStandard LVCMOS33
FIXED_IO_mio[9] of IOStandard LVCMOS33
FIXED_IO_mio[8] of IOStandard LVCMOS33
FIXED_IO_mio[7] of IOStandard LVCMOS33
FIXED_IO_mio[6] of IOStandard LVCMOS33
FIXED_IO_mio[5] of IOStandard LVCMOS33
FIXED_IO_mio[4] of IOStandard LVCMOS33
FIXED_IO_mio[3] of IOStandard LVCMOS33
FIXED_IO_mio[2] of IOStandard LVCMOS33
FIXED_IO_mio[1] of IOStandard LVCMOS33
and FIXED_IO_mio[0] of IOStandard LVCMOS33

 

A Route desing warning :

 

[DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are: LVCMOS18 (FIXED_IO_mio[53], FIXED_IO_mio[52], FIXED_IO_mio[51], FIXED_IO_mio[50], FIXED_IO_mio[49], FIXED_IO_mio[48], FIXED_IO_mio[47], FIXED_IO_mio[46], FIXED_IO_mio[45], FIXED_IO_mio[44], FIXED_IO_mio[43], FIXED_IO_mio[42], FIXED_IO_mio[41], FIXED_IO_mio[40], FIXED_IO_mio[39] (the first 15 of 38 listed)); LVCMOS33 (FIXED_IO_mio[15], FIXED_IO_mio[14], FIXED_IO_mio[13], FIXED_IO_mio[12], FIXED_IO_mio[11], FIXED_IO_mio[10], FIXED_IO_mio[9], FIXED_IO_mio[8], FIXED_IO_mio[7], FIXED_IO_mio[6], FIXED_IO_mio[5], FIXED_IO_mio[4], FIXED_IO_mio[3], FIXED_IO_mio[2], FIXED_IO_mio[1] (the first 15 of 16 listed));

 

 

Also, when trying to test a basic LwIP, I get no ethernet communication, so there's definitely something wrong with this

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Scholar stephenm
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9,708 Views
Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello Ronny,

 

I have replicated this issue, and I see these warnings too. However, these can be ignored.

User, can also supress these issues if they have verified thatt the system is working, by right clicking on the warning, and select supress.

 

In terms of the lwip, I have built a simple system (as per your steps), and exported to SDK. In SDK, I created a new LWIP Echo Server app. This works fine for me (see below).

 

I have also attached my working project. Can you test this on your side?

 

lwip_echo.png

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Scholar ronnywebers
Scholar
9,695 Views
Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello @stephenm, thanks for replicating the issue.

 

I tried with your project, but same result, I get no ping's back with 2015.3, only when running from 2015.2 or older versions ... very strange I must admit. I tried the same with a picozed board, but same results...

 

however address is correctly assigned etc. So i'm very puzzled at the moment. I also tried on a 100MBit and Gigabit switch, same result. 

 

here's some debug info to show IP is correctly assigned.

 

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
netif: IP address of interface set to 0.0.0.0
netif: netmask of interface set to 0.0.0.0
netif: GW address of interface set to 0.0.0.0
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
link speed for phy address 0: 1000
rxringptr: 0x00200758
txringptr: 0x00200714
rx_bdspace: 0x00300000
tx_bdspace: 0x00310000
netif: added interface te IP addr 0.0.0.0 netmask 0.0.0.0 gw 0.0.0.0
netif: setting default interface te
netif_set_ipaddr: netif address being changed
netif: IP address of interface te set to 172.16.101.18
netif: netmask of interface te set to 255.255.0.0
netif: GW address of interface te set to 172.16.1.8
Board IP: 172.16.101.18
Netmask : 255.255.0.0
Gateway : 172.16.1.8
TCP echo server started @ port 7

 

 

 

 

 

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Scholar stephenm
Scholar
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Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

 
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Scholar stephenm
Scholar
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Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hey, I have tried this again.

 

Here is what I see on the serial port:


-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation.
autonegotiation complete
link speed for phy address 0: 1000
DHCP Timeout
Configuring default IP of 192.168.1.10
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
TCP echo server started @ port 7

 

If I ping the board, I see:

 

Microsoft Windows [Version 6.1.7601]
Copyright (c) 2009 Microsoft Corporation.  All rights reserved.

C:\Users\stephenm>ping 192.168.1.10

Pinging 192.168.1.10 with 32 bytes of data:
Reply from 192.168.1.10: bytes=32 time<1ms TTL=255
Reply from 192.168.1.10: bytes=32 time<1ms TTL=255
Reply from 192.168.1.10: bytes=32 time<1ms TTL=255
Reply from 192.168.1.10: bytes=32 time<1ms TTL=255

Ping statistics for 192.168.1.10:
    Packets: Sent = 4, Received = 4, Lost = 0 (0% loss),
Approximate round trip times in milli-seconds:
    Minimum = 0ms, Maximum = 0ms, Average = 0ms

C:\Users\stephenm>

 

Have you access to wireshark, to see if any of the data is making it off of the board?

Or place an ILA on the Ethernet ports to see the activity here.

 

What Board rev are you using? Can you send me your project, Ill try it on my board.

 

Stephen

 

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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hey @stephenm, I'm using rev D

 

I've uploaded my project. I'm using VHDL for the wrapper, not sure if that makes the difference :-)

 

I'll put an ILA on the ethernet and check with wireshark on monday, I have to leave for the weekend. 

 

thanks already for the help so far!

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Scholar stephenm
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Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hey Ronny,

 

I downloaded your project and this works for me on my board. I can png the board.

Can you post your Host settings on your PC?

 

Can you also make sure that you have the firewall disabled?

 

Stephen

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Scholar ronnywebers
Scholar
9,631 Views
Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello Stephen, thanks for verifying my project, that's one step further!

 

my firewall etc. is disabled, I just switch between my 2015.2 and 2015.3 projects, without modifying anthing (host, firewall, cabling, ...). I can ping with the Zedboard when launching from 2015.2, but not from 2015.3 

 

I use DHCP, so the board gets an address assigned by our network server - do you use fixed IP maybe, with a direct connection from your pc to your board? I'll give that a try today.

 

 

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Scholar ronnywebers
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

I'm sorry - I can see you have a DHCP timeout, so you must be using fixed IP. Do you use direct connection between your pc and zedboard, or through a switch? If it's a switch / router, a 100MBit or 1Git one? I've already tried both.

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Scholar ronnywebers
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello,

 

After endless retries, and switching between 2015.2 and 2015.3 versions of Vivado, I have - by accident I guess - 'solved' the problem.

 

I always launch my SDK applicatoins using the debugger as follows :

 

Right-click on the application -> Debug as -> Launch on hardware (System debugger)

 

At a certain moment I saw in the SDK Log window the following error in red :

 

Error occured during Prog B register check

 

I could not find any explanation on the web, so I decided to launch my application once again using the GDB debugger. Still I am not sure about the exact difference between both debuggers, but anyway, the red error was gone, and guess what ... my ping suddenly worked.... inexplicable if you ask me, seems like some very obscure bug.

 

Afterwards I tried again using System Debugger, and that also works fine.

 

So @stephenm thanks for all your help, seems like I was stuck on a very strange Vivado bug... much time wasted, but I can continue now.

 

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Scholar stephenm
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Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

You shouldnt need to have the PL configured if you are just using the PS. sounds like a bug

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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

ok @stephenm - you're right - but out of habbit I always program the PL ... so that was maybe the problem?

 

If I may : what is the main difference between the system debugger and GDB ?

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Scholar stephenm
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Registered: ‎05-06-2012

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

well, if there is a bit in the hdf (the hdf is the container file, like a zip which contains all the files exported to sdk from Vivado. this sits in the hw_platform), then the tools will try to program. Even though in your case it is just a wrapper.

 

system debugger is a tcf based protocol (which is thread based) so can execute difference transaction in parallel.

The gdb work serially. so the system debugger is potentially faster. the system debuuger is recommended over the gdb.

However, some users still like the gdb debugger. The system debugger, has all the same features as the gdb

Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

@stephenm I was too quick with my answer too I guess : if I look at my block diagram, I think I do have to program the PL, as FCLK_CLK0 is connected to M_AXI_GP0_ACLK ?

 

I could of course have disabled the M_AXI_GP0 interface, ast it is not used. But by default, if you put the Zynq IP block in a block diagram, it is enabled.

 

 

 

 

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BD.jpg
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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: Vivado 2015.3 strange synth, place & route warnings with Zedboard

Hello @stephenm, I think I have finally nailed the exact problem. I found a way to reproduce it systematicaly :

 

the problem comes from 'relaunching' the application in SDK a 2nd time, without powering down the board (some kind of reset issue?)

 

So behaviour of what I describe below is the same in2015.2 and 2015.3, and the same on Zedboard and Picozed

 

* build the minimal Zynq system (GEM0) as described in previous mails

* direct cable connection, fixed IP

* don't download the bistream (not really needed as you said before)

* launch the 'out-of-the-box' LwIP application using system debugger

* -> ping is ok

 

then ....

 

* halt the application, and relaunch

-> ping is not ok 

 

note1 : full 'disconnect' and 'relaunch with sytem debugger' does not solve the issue

 

note 2 : with Wireshark I can still see DHCP broadcasts from the Zynq / LwIP, with it's fixed IP address 192.168.1.10. So the board is definitely running after this '2nd launch', but not answering to ping's. Could this be some ARP issue in the LwIP stack?

 

then to solve this situation ...

 

* power down the board

* relaunch the application

-> ping is ok again!

 

so looks like some warm reset issue (?) 

 

btw, I think the issue 'Error occured during Prog B register check' that I had resolved by switching to the GDB and back to System Debugger was some strange, non-reproducible error (?)

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