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Observer israelgr
Observer
1,743 Views
Registered: ‎04-14-2018

Vivado 2018.2.1 : Non-module Files

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Hi,

I'm using Vivado 2018.2.1 (update 1), my target FPGA is V7 690 (the VC709 EV board).

I made a minor change in one of my project's file, and suddenly all my projects become a "Non-module Files".

I ran the command check_syntax in the Tcl Console and got: INFO: [Vivado 12-4796] No errors or warning reported.

In the Messages tab, I do see some critical warnings mark as [HDL 9-946], [HDL 9-797], and [HDL 9-187] which there meaning is unclear, so I don't know how to solve them.

 

Please advise.

 

Thanks,

Israel.

 

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Observer israelgr
Observer
1,623 Views
Registered: ‎04-14-2018

回复: Vivado 2018.2.1 : Non-module Files

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Hello graces, brimdavis,

I'm currently working on Windows 10 version of Vivado 2018.2.1, and the code doesn't seem to have a real syntax problem.

Changing the srcscanner's "hierarchy update" to semi-manual (Automatic update, Manual compile order) or manual (No update, Manual compile order) as the article AR#69846 suggested:
"When using either of the Manual modes, Vivado will send all of the files in the source fileset to the Synthesis (or Simulation) process being run and the Synthesis process will do a separate parse of the files to determine dependencies."
Didn't work, since Vivado keep saying that there are no files in the project.

Finally, I moved the project back to Vivado 2017.2, and I started to get some significant leads to what bothers Vivado:
1) Brackets - I'm using a generic value to define in synthesis time the size of a vector:
signal VECTOR_NAME             : std_logic_vector((GENERIC_VALUE-1) downto 0);
> Vivado wish to have it like that: signal VECTOR_NAME             : std_logic_vector(GENERIC_VALUE-1 downto 0);
I'm also using a for...generate loops, like: for "i" in ((GENERIC_VALUE-1) downto 0) generate
> Vivado wish to use: for i in GENERIC_VALUE-1 downto 0 generate
2) Re-use the variable "i" in for...generate - in one of the modules I use two for...generate statements. Both of them use the variable "i" as an index, Vivado didn't like the second implementation.

>> Once I replaced the index letter and removed the brackets, all the files returned to the project in the correct hierarchy (I used: Automatic Update and Compile order). then, I copied these changes back to 2018.2.1, and it works well also.
I start to revert the changes to find what causes the problem in the first place; I noticed that the brackets on the second for…generate loop (not the index letter “i”) are the root cause.

 

Before all of these changes, the 2018.2.1 version also made problems with assigning -  InputSignal => SignalA & SignalB (in a port map declaration). It also made a problem with the function gf16mult (as shown in the warning screenshot) due to input1 as a 4 bits signal and input2 as 4 bits constant.

 

Thank you very much for your help,

Israel.

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Xilinx Employee
Xilinx Employee
1,718 Views
Registered: ‎07-16-2008

回复: Vivado 2018.2.1 : Non-module Files

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Can you post the detailed Critical Warning messages?

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Observer israelgr
Observer
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Registered: ‎04-14-2018

回复: Vivado 2018.2.1 : Non-module Files

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Please see the attached file.

 

Thanks,

Israel.

critical warning.jpg
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Xilinx Employee
Xilinx Employee
1,678 Views
Registered: ‎07-16-2008

回复: Vivado 2018.2.1 : Non-module Files

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The messages complain about the port matching in entity.

Take the first message for example, is "divider_i" a valid port name in the target entity? It looks more like an instance name.

How did you edit the files? Could it be due to some non-English characters?

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Scholar brimdavis
Scholar
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Registered: ‎04-26-2012

回复: Vivado 2018.2.1 : Non-module Files

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@israelgr  'suddenly all my projects become a "Non-module Files"'

It looks like the problem is that Xilinx's srcscanner has crashed, see the 'filemgmt 20-2001' errors.

This buggy srcscanner program was introduced in 2017.x, and has caused many problems; you've probably got a source code construct (or typo) that is crashing it.

Try the workarounds suggested here:

  2017.x Vivado - The hierarchy source view in Vivado 2017.x is incorrect or takes a long time to update

  https://www.xilinx.com/support/answers/69846.html

-Brian

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Observer israelgr
Observer
1,624 Views
Registered: ‎04-14-2018

回复: Vivado 2018.2.1 : Non-module Files

Jump to solution

Hello graces, brimdavis,

I'm currently working on Windows 10 version of Vivado 2018.2.1, and the code doesn't seem to have a real syntax problem.

Changing the srcscanner's "hierarchy update" to semi-manual (Automatic update, Manual compile order) or manual (No update, Manual compile order) as the article AR#69846 suggested:
"When using either of the Manual modes, Vivado will send all of the files in the source fileset to the Synthesis (or Simulation) process being run and the Synthesis process will do a separate parse of the files to determine dependencies."
Didn't work, since Vivado keep saying that there are no files in the project.

Finally, I moved the project back to Vivado 2017.2, and I started to get some significant leads to what bothers Vivado:
1) Brackets - I'm using a generic value to define in synthesis time the size of a vector:
signal VECTOR_NAME             : std_logic_vector((GENERIC_VALUE-1) downto 0);
> Vivado wish to have it like that: signal VECTOR_NAME             : std_logic_vector(GENERIC_VALUE-1 downto 0);
I'm also using a for...generate loops, like: for "i" in ((GENERIC_VALUE-1) downto 0) generate
> Vivado wish to use: for i in GENERIC_VALUE-1 downto 0 generate
2) Re-use the variable "i" in for...generate - in one of the modules I use two for...generate statements. Both of them use the variable "i" as an index, Vivado didn't like the second implementation.

>> Once I replaced the index letter and removed the brackets, all the files returned to the project in the correct hierarchy (I used: Automatic Update and Compile order). then, I copied these changes back to 2018.2.1, and it works well also.
I start to revert the changes to find what causes the problem in the first place; I noticed that the brackets on the second for…generate loop (not the index letter “i”) are the root cause.

 

Before all of these changes, the 2018.2.1 version also made problems with assigning -  InputSignal => SignalA & SignalB (in a port map declaration). It also made a problem with the function gf16mult (as shown in the warning screenshot) due to input1 as a 4 bits signal and input2 as 4 bits constant.

 

Thank you very much for your help,

Israel.

View solution in original post

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Observer peterzh2018
Observer
442 Views
Registered: ‎08-16-2018

回复: Vivado 2018.2.1 : Non-module Files

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can't revieve any axi dma intrruput on vivado 2018.2.1?  why?  the project woks well on 2018.2. what's the diffrence between them?

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