Vivado 2019.2 : issue to create Block Design

[thomas_b]

Hello,

I installed VIVAVO 2019.2 on windows 10

I created a new project with ALVEO 200 board

I ask to “Create Block Design”

I launch “set clk_wizard [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz clk_wizard ]”

I receive error:

ERROR: [IP_Flow 19-2373] Cannot identify default part.

ERROR: [Common 17-39] 'xit::add_dynamic_interface' failed due to earlier errors.

CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2019.2/data/ip/xilinx/clk_wiz_v6_0/elaborate/ports.xit': ERROR: [Common 17-39] 'xit::add_dynamic_interface' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).

ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'clk_wizard'. Failed to generate 'Elaborate Ports' outputs:

ERROR: [IP_Flow 19-2373] Cannot identify default part.

ERROR: [IP_Flow 19-2373] Cannot identify default part.

ERROR: [IP_Flow 19-2373] Cannot identify default part.

ERROR: [BD 41-134] No portmaps are present on the interface: clock_CLK_IN1

ERROR: [BD 41-951] Parameter FREQ_HZ not found on /clk_wizard/clk_in1

ERROR: [BD 41-951] Parameter FREQ_HZ not found on /clk_wizard/clk_in1

ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

ERROR: [BD 41-1273] Error running post_config_ip TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    ::xilinx.com_ip_clk_wiz_6.0::post_config_ip Line 62

create_bd_cell: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2063.684 ; gain = 1110.918

ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

I push the button “add IP”

I relaunch “set clk_wizard [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz clk_wizard ]”

And it work !!

I think that there is an issue at the opening of VIVADO (which do not link the IPs).

Someone has the same issue?

How to solve? Because, when I reopen the project, I have the same issue

Thanks

[ram.pillai@williamsf1.com]

Same issue for me but for ZCU104 board having Zynq UltraScale+. Reinstalled board repositories but still no luck. 

[thomas_b]

With Vivado 2019.1, no issue.

[andriy_rachek · Accepted solution]

Hi,
I've had the same problem (but for XC7A200 chip): my Tcl code where clk_wiz is used did'n work with Vivado 2019.2.

My solution is:
Run Xilinx Information Center, choose "Manage Installs" tab. Under "Xilinx Design Tools Vitis Unified Software Platform 2019.2" press "Add Tools/Device".

Then press "Next" untill "Select Extra Content" window will be shown. Under "Device / Device for Custom Platforms" choose all 7 series family. Press "Next". New devices will be installed.

After this my Tcl code runs without errors.

[thomas_b]

Hello andriy_rachek,

Just adding the "7 series family" devices is resolving the trouble.

Thanks a lot, I was totally stuck.

[olupj]

This was an issue with the initial release of 2019.2 (SW Build: 2700185 on Thu Oct 24 18:45:48 MDT 2019).

I had the issue targeting the RFSoC (migration from 2019.1 or creating new design in 2019.2, same error).

When I updated to the latest build (SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019) it works.

-Jerry

[kahalani]

Hi All,

Just to make it clear, if u get above error u should install 7 series devices and it fix the problem regardless device u use

BR

Itamar