05-11-2016 05:44 AM
I am using Vivado 2015.4 and trying to package my IP block. This IP block consists of multiple channels: each channel has AXIS slave at the input and AXIS master at the output. The amount of channels is controlled by parameter. Here is sample code:
module sample_ip # (
parameter integer C_CHANNELS_COUNT = 2,
parameter integer C_AXIS_DATA_WIDTH = 16
// an array of AXIS slave buses for input channels
input logic [C_CHANNELS_COUNT-1:0] s_axis_ch_input_aclk,
input logic [C_CHANNELS_COUNT-1:0] s_axis_ch_input_aresetn,
output logic [C_CHANNELS_COUNT-1:0] s_axis_ch_input_tready,
input logic [C_CHANNELS_COUNT-1:0][C_AXIS_DATA_WIDTH-1:0] s_axis_ch_input_tdata,
input logic [C_CHANNELS_COUNT-1:0] s_axis_ch_input_tvalid,
// an array of AXIS master buses for output channels
input logic [C_CHANNELS_COUNT-1:0] m_axis_ch_output_aclk,
input logic [C_CHANNELS_COUNT-1:0] m_axis_ch_output_aresetn,
input logic [C_CHANNELS_COUNT-1:0] m_axis_ch_output_tready,
output logic [C_CHANNELS_COUNT-1:0][C_AXIS_DATA_WIDTH-1:0] m_axis_ch_output_tdata,
output logic [C_CHANNELS_COUNT-1:0] m_axis_ch_output_tvalid
// generate the same logic for each channel
for (i = 0; i < C_CHANNELS_COUNT; i = i + 1) begin: axis_channel
// there will be processing here, but for now just delay input for one clock cycle
always @(posedge s_axis_ch_input_aclk[i]) begin
m_axis_ch_output_tdata[i] <= s_axis_ch_input_tdata[i];
m_axis_ch_output_tvalid[i] <= s_axis_ch_input_tvalid[i];
s_axis_ch_input_tready[i] <= m_axis_ch_output_tready[i];
When I set the C_CHANNELS_COUNT to 1 and package this up, I get a IP module which can be used in Vivado GUI block design and has a single channel with one AXIS slave input and one AXIS master output. The AXIS interfaces data width is 16, which is correct. So far so good
Now when I set C_CHANNELS_COUNT to 2 and package this up, instead of IP module with two AXIS slaves and two AXIS masters I get a module with single slave and single master, but their signals sizes are doubled. For example AXIS interface data is now 32.
What should I do to get multiple AXIS interfaces being inferred instead of single one with multiplied width? I am kind of after a behaviour which Xilinx AXI Interconnect has.
05-11-2016 12:27 PM
05-12-2016 12:49 AM
Thanks for coming back to me. I don't mind if I have to run tcl scripts along with changing parameter name as long as it does the job. Can you give me more pointers about what this tcl script contents may be please?
05-12-2016 01:36 PM
05-13-2016 02:13 PM
What Xillinx IP are you trying to connect to?
The axi_interconnect module (for AXI buses) is available as a nice parameterized IP from Xilinx. See DS768 (you may need to go back to an older version of Vivado to get this, Xilinx is attempting to bury this IP, IMHO). Supports N Master, N slaves, and has portlist parameterized similar to how you've done.
Using that, there's no reason for (the silly) IP integrator.
As to AXIS bus - what sort of IP? For that - since it's point-to-point we just hook things up as neccesary in RTL.