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Way
Adventurer
Adventurer
1,886 Views
Registered: ‎10-19-2020

Vivado Warning [IP_Flow 19-3571] IP 'design_xx' is restricted: * Module reference is stale and needs refreshing.

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Hi,

I created a RTL modules and used module reference method to add the RTL modules into the block design in IP integrator. Once I tried to synthesize the design, there is a warning message mentioned "IP 'design_xx' is restricted: module reference is stale and need "refreshing". 

I did not able to find any solution about that and the root cause for this warning. I did not update the module or modifying the module. Wonder if why this warning appear and may I know how do we resolve this warning?

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ashishd
Xilinx Employee
Xilinx Employee
1,654 Views
Registered: ‎02-14-2014

Hi @Way ,

This issue is already reported to IP Flows development team through CR. Supposed to be fixed in next Vivado release (this is tentative and subject to change).
The warning is redundant and can be safely ignored.

Regards,
Ashish
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ashishd
Xilinx Employee
Xilinx Employee
1,787 Views
Registered: ‎02-14-2014

Hi @Way ,

Can you attach your RTL modules here? And which version of Vivado it is?

Regards,
Ashish
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Way
Adventurer
Adventurer
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Registered: ‎10-19-2020

Hi @ashishd 

Sorry for the late reply. Attached is the RTL modules.

The version I am using is Vivado 2020.1

Hope to hear from you soon. 

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ashishd
Xilinx Employee
Xilinx Employee
1,721 Views
Registered: ‎02-14-2014

Hi @Way ,

I created project and added source file which you've attached to it. I then created module reference block design cell for this RTL and synthesized this project. Synthesis was successful without any issue. So few things to check -

1. Are you migrating this design from some earlier Vivado version?

2. Is this source file present in some revision control system wherein it can be edited and managed by several people?

3. Can you try adding command - update_module_reference {<list of module references in your block design>} before synthesizing the design? In this case, command should be -

update_module_reference design_1_vid_edid_0_0

Regards,
Ashish
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Way
Adventurer
Adventurer
1,713 Views
Registered: ‎10-19-2020

Hi @ashishd ,

Thanks for the looking into this. Below is my answer to the questions

1. No

2. No

3. I tried to run the command in tcl console before synthesis the design. I am still seeing the warning.

At the same time, it is weird that why you didn't encounter the warning. I start from scratch with a new project, added the RTL to be a module in BD design, generate output product and create HDL wrapper. After that, I try to synthesize the design. I am still seeing the warning as shown below:

 

warning.PNG
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ashishd
Xilinx Employee
Xilinx Employee
1,703 Views
Registered: ‎02-14-2014

Hi @Way ,

I was unable to see the warning as I was generating output products of block design in Global mode and then performing top level Synthesis.

As per your latest snapshot, when I gave a try with ooc per IP (default) mode and I am able to reproduce this problem. Let me investigate further and will update. 

Regards,
Ashish
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ashishd
Xilinx Employee
Xilinx Employee
1,655 Views
Registered: ‎02-14-2014

Hi @Way ,

This issue is already reported to IP Flows development team through CR. Supposed to be fixed in next Vivado release (this is tentative and subject to change).
The warning is redundant and can be safely ignored.

Regards,
Ashish
----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------

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Way
Adventurer
Adventurer
1,620 Views
Registered: ‎10-19-2020

Hi @ashishd 

Thanks for the information.

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aesanchez
Visitor
Visitor
956 Views
Registered: ‎04-03-2019

Hi Ashish

I am getting the same problem. I am using Vivado 2020.2. Do the HDL sources need to be in a specific place besides sources?

 

Alberto

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ashishd
Xilinx Employee
Xilinx Employee
901 Views
Registered: ‎02-14-2014

Hi @aesanchez ,

This issue is fixed in upcoming Vivado release. HDL sources need not necessarily be at some separate location. 

Regards,
Ashish
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RustyWiire31
Visitor
Visitor
833 Views
Registered: ‎06-01-2021

@ashishd  Do you mean in the Vivado 2020.3 version ? Because I have also this issue with Vivado 2020.2 and I don't know if the Vivado 2020.3 will fix this issue

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ashishd
Xilinx Employee
Xilinx Employee
813 Views
Registered: ‎02-14-2014

@RustyWiire31  I meant 2021.1

Regards,
Ashish
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rchokshi
Visitor
Visitor
678 Views
Registered: ‎11-29-2017

Hi Ashish,

Do you know, Release date of 2021.1? Thanks in advace. 

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ashishd
Xilinx Employee
Xilinx Employee
523 Views
Registered: ‎02-14-2014

Hi @rchokshi ,

2021.1 is released. Please check and feel free to update regarding your observations for this issue.

Regards,
Ashish
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