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Newbie rpkh
Newbie
4,811 Views
Registered: ‎08-08-2013

Vivado bug; auto create vhdl file

The creation of a new vhdl source via the project manager (Add sources) is not done correctly.
After defining the module, immediately a syntax error is generated for the file.

Opening the file reveals the error. "entity <source name> is" is defined twice.

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Xilinx Employee
Xilinx Employee
4,808 Views
Registered: ‎09-20-2012

Re: Vivado bug; auto create vhdl file

Hi,

 

Welcome to Forums.

 

This is a known issue in vivado 2013.2. It has been reported to our development team for fix.

 

As a workaround for now, edit the file manually after creating the VHDL source file.

 

Cheers,

Deepika.

Thanks,
Deepika.
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