03-13-2015 10:28 AM
I am having problems synthesising the SRIO GEN2 IP in a Vivado block diagram design.
The IP has a differential clock input which I am connecting directly to two clock input pins
I am initially attempting to use the 4 lane PCIE connector on the ZC706 for a 4 channel SRIO i/f. clocked by what would have been the PCIE clock.
i get :-
[Drc 23-20] Rule violation (REQP-1619) IBUFDS_GTE2_driven_by_IBUF - IBUFDS_GTE2 design_1_i/srio_gen2_0/inst/srio_clk_inst/u_refclk_ibufds pins I and IB should be driven by IBUFs.
the clock buffer in the IP catalogue doesn't seem to have a diff-in/ diff-out option assuming that is what s needed?
If I create an external port from the IP on the top level, it creates a single DIFF port (how do I assign his to two pins?)
Is there an easy way to get round this? please try to resist referring to U901 ;-)
On another note, I am a bit confused if Vivado is happy to instantiate my VHDL IP into a Verilog top level design.
The reason being that the SRIO GEN2 core is verilog and I am writing my code in VHDL.
what is the best way to do this?
03-13-2015 08:14 PM
03-16-2015 06:36 AM
Thanks for the response.
I wasn't running synthesis in out of context mode.
I did find that I had not recreated the wrapper and the clock inputs were not listed.
After recreating a verliog wrapper the clock pins now connect.
This does lead me to my other question regarding the fact that Ihave some custom IP blocks written in VHDL.
Is Vivado supposed to be able to handle Verilog and VHDL together?
03-16-2015 06:59 AM
Vivado synthesis has mixed language support. I suspect that the wrapper file may not be up to date which is the reason you saw the issue.
03-23-2015 09:33 PM
I hope your queries are answered. Please close this thread by marking the answer.