06-11-2019 05:46 AM
There is following constraint in .xdc:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets spis_sck_18_IBUF]
Synthesis tool gets this warning:
[Vivado 12-507] No nets matched 'spis_sck_18_IBUF'. ["/home/pyo/proj_Vivado/isg001_logic/isg001_logic.srcs/constrs_1/new/constraints_1.xdc":375]
where 375 is the numeber of line where above mentioned costraint is located in .xdc.
Here is the result of search on nets "*spis_sck*"
Any comments ?
06-12-2019 06:36 PM
Is it recognized if you open synthesized design and run the get_nets command from Tcl console？
06-12-2019 06:57 PM
Hi @pavel_47 ,
Please refer to this AR https://www.xilinx.com/support/answers/54799.html
Hope it help you.
06-13-2019 12:16 AM
Here is what happens when I run get_nets in Tcl console when synthesized design is opened:
So, the net named spis_sck_18_IBUF does exist in synthesized netlist, but isn't recognized in .xdc.