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Voyager
Voyager
436 Views
Registered: ‎05-30-2018

Vivado doesn't recognize net that exists

Hello,

There is following constraint in .xdc:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets spis_sck_18_IBUF]

Synthesis tool gets this warning:

[Vivado 12-507] No nets matched 'spis_sck_18_IBUF'. ["/home/pyo/proj_Vivado/isg001_logic/isg001_logic.srcs/constrs_1/new/constraints_1.xdc":375]

where 375 is the numeber of line where above mentioned costraint is located in .xdc.

Here is the result of search on nets "*spis_sck*"

spis_sck_18_IBUF_search.png

Any comments ?

Thanks.

 

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Moderator
Moderator
403 Views
Registered: ‎07-16-2008

Is it recognized if you open synthesized design and run the get_nets command from Tcl console?

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Xilinx Employee
Xilinx Employee
399 Views
Registered: ‎02-27-2019

Hi @pavel_47 ,

Please refer to this AR https://www.xilinx.com/support/answers/54799.html

Hope it help you.

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Voyager
Voyager
379 Views
Registered: ‎05-30-2018

Here is what happens when I run get_nets in Tcl console when synthesized design is opened:

get_nets spis_sck_18_IBUF
spis_sck_18_IBUF

So, the net named spis_sck_18_IBUF does exist in synthesized netlist, but isn't recognized  in .xdc.

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