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Participant
Participant
1,371 Views
Registered: ‎06-28-2018

Vivado infers nets such that I have Multiple Driver Net problems, despite my custom IP not having that issue

Hello,

 

My name is Julian and currently, I'm building a custom IP in VHDL using Vivado 2018.2. The target is a Zynq UltraScale+ ZC102.

 

The IP has an AXI4-Lite port and an AXIS Master and Slave as well. I have built my IP such that it has a core, that core is wrapped with the Vivado generated AXI4-Lite driver altogether with an AXIS Finite State Machine I have included. The result is an IP with the described ports.

 

Now, I have exported that IP using the Vivado IP packaging wizard and instantiated the IP in a Block Design. For the record, I have an identical IP but I've written it within Vivado HLS. I have placed both IPs in the block design to verify that both functions properly and produce the same output. That block design has a typical PS + DMA + ILAs architecture. 

 

¿Where do my problems start? During the implementation of that block design. The implementation fails with a Multiple Driver Net problem. I have run the synthesis DRC (as the implementation does not go through) with the same result: the P[x] signal has apparently multiple drivers... signals I have no control over (as it seems, I did not write them explicitly). 

 

Errors reported by DRC are as follows:

 

Net P[0] has multiple drivers: M_AXIS_TDATA[16]_INST_0.O, DPS_OUTPUT_INST.P[0].

Net P[10] has multiple drivers: M_AXIS_TDATA[26]_INST_0.O, DPS_OUTPUT_INST.P[10].

 

This is confusing to me, as the project that I use for the IP design using RTL does not suffer from that problem. I have read posts in this forum that describe similar problems, but most of the times they were solved by solving the RTL design. Yet, I don't have multiple processes driving one single signal, not only out of principle, also because the synthesizer would tell me about it and it would not let me simulate the IP. I have yet to find that error at the IP design level instead of the block design level, and mostly, because the signals described are not signals that I have put there. For example, P[x] and DPS_OUTPUT_INST.P[x] are not nets that I have placed there by hand so to speak.

 

Basically, I have managed to simulate the IP using an RTL testbench, but include it in a block design, and the implementation phase fails miserably. I even have run the implementation phase for the RTL project only, with success, even though it is of no use to me in that state.

 

I don't know where to continue my search, to be honest. I have a couple of ideas but I'm foreseeing that they will fail.

 

¿Any ideas? ¿What am I missing? If you need more info, ask and you shall receive.

 

I have attached an image of what I think is the critical point in the schematic, illustrating the multiple driver problem. 

 

Regards,

Julian

 

edit; modified a few phrases.

edit2; added info.

 

 

 

Captura.PNG
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Scholar
Scholar
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Registered: ‎08-07-2014

Re: Vivado infers nets such that I have Multiple Driver Net problems, despite my custom IP not having that issue

@julian.spahr,

 

Hi,

You say the IP as a standalone module does not have the problem.

 

Then I would also re-check the top level port connections of the module where the IP is instantiated. May be a trivial human error?

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Participant
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Registered: ‎06-28-2018

Re: Vivado infers nets such that I have Multiple Driver Net problems, despite my custom IP not having that issue

Hi @dpaul24,

 

I do hope it is a trivial human error. Connected to the IP (window_axis_top_0) are AXIS type interfaces on both sides, plus the mentioned AXI-Lite (as shown in the attached figure). As you can see, the IP is connected to FIFOs on those sides.

 

As an update, in an effort to solve the error, I have been updating the IP such that I'm not instantiating that many modules inside of it. I'm basically destroying a few hierarchy levels to ease up the schematic. I'm hoping that Vivado infers other logic as a response to it.

 

The original Multiple Driver Net problem occurs at a lower hierarchy level than my IP (inside of it) but right before driving M_AXIS_TDATA.

 

Since I haven't found the origin of my problem, I will re-generate the IP and the block design and investigate the resulting schematic.

 

Thanks!

Captura0.PNG
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