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Explorer
Explorer
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Registered: ‎01-15-2008

Why does Vivado reject my bi-directional ports?

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Vivado 2018.3, custom board.  I have a custom IP with two bi-directional IO ports.  I ask Vivado to make these external, and it does:


Capture.JPG

But when I synthesize the design, Vivado puts in an OBUF, not an IOBUF.

Thanks,

Rick

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Scholar
Scholar
743 Views
Registered: ‎04-26-2012

@rikraf   "a colleague of mine used the same IP core instantiated in a Vivado (same version, I believe) block diagram, and got an IO port..... Must be a setting somewhere."

Vivado doesn't handle lower level tristate and bidirectional ports correctly when using either Out-of-Context flows or certain hierarchial synthesis settings, as under those conditions it can not transmogrify the single wire port into the multiple wires needed to build these constructs in hardware.

See the following for more info:

  https://forums.xilinx.com/t5/Synthesis/Setting-flatten-hierarchy-none-causes-generate-bitstream-to-fail/m-p/797580/highlight/true#M22893

  https://forums.xilinx.com/t5/Implementation/tristate-logic-not-implemented-in-2016-4/m-p/742355/highlight/true#M16967

  AR# 46743 Would Vivado Synthesis be able to infer tristate logic in a lower level module when flatten_hierarchy is set to none?

 

-Brian

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Highlighted
779 Views
Registered: ‎01-22-2015

Hi Rick,

“No IOBUFs for Custom IP” seems to be one of the unwritten rules.  A solution is to have signal_I (input), signal_O (output), and signal_T (tri-state) ports on your custom IP – and to connect these to an IOBUF, which in turn, connects to FPGA pins at the top-level of your design.

Mark

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Explorer
Explorer
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Registered: ‎01-15-2008

Right, and that's what I usually do!  But in fact a colleague of mine used the same IP core instantiated in a Vivado (same version, I believe) block diagram, and got an IO port.....  Must be a setting somewhere.  I'm loath to dig into this core.

Thanks

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Scholar
Scholar
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Registered: ‎06-20-2017

Look at naming convention on QSPI IP.  If you follow that I think it *might* auto instantiate IOBUF.  Hope this helps.  (But be warned, it's been awhile and I am going from memory). 

 

EDIT:  Based on comment below, I also remember I had to turn off OOC to get it to infer an IOB correctly.

Mike
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Scholar
Scholar
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Registered: ‎04-26-2012

@rikraf   "a colleague of mine used the same IP core instantiated in a Vivado (same version, I believe) block diagram, and got an IO port..... Must be a setting somewhere."

Vivado doesn't handle lower level tristate and bidirectional ports correctly when using either Out-of-Context flows or certain hierarchial synthesis settings, as under those conditions it can not transmogrify the single wire port into the multiple wires needed to build these constructs in hardware.

See the following for more info:

  https://forums.xilinx.com/t5/Synthesis/Setting-flatten-hierarchy-none-causes-generate-bitstream-to-fail/m-p/797580/highlight/true#M22893

  https://forums.xilinx.com/t5/Implementation/tristate-logic-not-implemented-in-2016-4/m-p/742355/highlight/true#M16967

  AR# 46743 Would Vivado Synthesis be able to infer tristate logic in a lower level module when flatten_hierarchy is set to none?

 

-Brian

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Explorer
Explorer
711 Views
Registered: ‎01-15-2008

Yes!  thank you.  One needs to "Regenerate Output Products" and select "Global".  Then Vivado can figure out what you want.

Capture.JPGThis works

Thanks,

Rick

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