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11-23-2015 05:33 PM - edited 11-23-2015 05:34 PM
Dear Xilinx -
Is there a solution in the works for this problem? Is it even being discussed internally? I'm going to post this question every few months as the Vivado quarterly releases tick by with no fix and no viable workaround.
11-23-2015 07:33 PM
Hi @rjsefton
This is Windows OS limitation.
Please check the following AR where some suggestions are given to workaround this.
http://www.xilinx.com/support/answers/52787.html
11-23-2015 07:33 PM
Hi @rjsefton
This is Windows OS limitation.
Please check the following AR where some suggestions are given to workaround this.
http://www.xilinx.com/support/answers/52787.html
11-23-2015 08:24 PM
Quoting from the AR you linked:
"The error is most often seen when generating IP cores and archiving, due to the deep hierarchical structure of some of the IP ..."
Question: Who or what creates that "deep hierarchical structure" in the IP, and in the Vivado project structure?
Answer: Vivado does!
This is not an OS problem. It's a Xilinx problem for not designing Vivado to work within the limits of the OS. It should not be the user's responsibility/burden to work around this oversight by Xilinx.
I've been doing this stuff for a very long time and I have never encountered the Windows path name length limit under any circumstances with any other EDA tool. I didn't even know the limit existed, and clearly neither did Xilinx. Please don't try to paint this as a Windows problem. It's on you guys to do something about it. Flatten the project hierarchy and the problem is solved.
To repeat my original question: Is this even being discussed within Xilinx, or is AR 52787 the official non-solution?
11-23-2015 10:26 PM
Hi @rjsefton,
I haven't come across any of your earlier post regarding same issue.
I took this post further and already started discussion internally. I will keep you updated on progress.
Thanks,
Yash
11-24-2015 07:33 AM
Thanks, Yash. By the way, I have posted about this before:
It's a nasty problem to have to fix after the fact, but something has to be done about it.
Bob S.
11-24-2015 08:20 PM
Hi @rjsefton
I meant that the limitation is coming from Windows OS.
There are multiple CRs around this and the development team is working on finding real time solution. Till then, please use the workaround give in that AR.
12-01-2015 05:52 AM
I received an email nag this morning from Xilinx asking me to mark this thread as resolved. It isn't, but I'll mark it anyway. Keeping my fingers crossed that Xilinx finds a way to fix this in Vivado.
12-01-2015 02:52 PM
There is a new feature to Vivado called "Core Container" which is an option available for IP. This feature is documented in UG896 Design with IP. Basically it is the zipping up of the IP directory into a binary which Vivado directly access during synthesis and implementation. On Windows using the core container should address many of the path length issues that are hit with the Xilinx IP and directory path lenghts. Since Vivado directly access the binary (i.e. does not extract to a temporary area on disk) the "paths" can be longer than the length supported in Windows.
Please give core container a try.
Regards,
Cyrus
05-08-2019 06:30 AM
Got the same problem. Solved it with longpathtool.
Please, write if it works for you too.