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Registered: ‎01-11-2014

Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Hi guys,

 

I am trying to follow this tutorial http://www.xilinx.com/support/documentation/application_notes/xapp794-1080p60-camera.pdf. using the Zynq-7000 All Programmable SoC Video and Imaging Kit.

 

I did got the reference design to work. However, when I tried to rebuild the hardware platform(page 43), after running the build_camera_design.tcl file(page 45), my vivado shows the errors below:

 

Synthesis error

 

 

Error: [BD 41-1030] Generation failed for the IP Integrator block /fmc_imageon_vita_receiver_1

 

Critical warnings

 

Synthesis
Implementation
Design Initialization
[Project 1-486] Could not resolve non-primitive black box cell 'afifo_32_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/afifo_32.vhd":121]

[Project 1-486] Could not resolve non-primitive black box cell 'pulse_regen_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/framestart2_regen_l/K7_GEN.pulse_regen_k7_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/pulse_regen.vhd":121]

[Project 1-486] Could not resolve non-primitive black box cell 'afifo_64i_16o_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/afifo_64i_16o.vhd":120]

 

Implementation errors

 

Synthesis
[Netlist 29-72] Incorrect value 'zynq' specified for property 'SIM_DEVICE'. Expecting type 'string' with possible values of '7SERIES,VIRTEX4,VIRTEX5,VIRTEX6'. The system will either use the default value or the property value will be dropped. Please verify your source files. ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/iserdes_clocks.vhd":1204]

[Netlist 29-72] Incorrect value 'zynq' specified for property 'SIM_DEVICE'. Expecting type 'string' with possible values of '7SERIES,VIRTEX4,VIRTEX5,VIRTEX6'. The system will either use the default value or the property value will be dropped. Please verify your source files. ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/iserdes_clocks.vhd":1204]

Implementation
Design Initialization
[Project 1-486] Could not resolve non-primitive black box cell 'afifo_32_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/afifo_32.vhd":121]

[Project 1-486] Could not resolve non-primitive black box cell 'pulse_regen_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/framestart2_regen_l/K7_GEN.pulse_regen_k7_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/pulse_regen.vhd":121]

[Project 1-486] Could not resolve non-primitive black box cell 'afifo_64i_16o_k7' instantiated as 'U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l' ["m:/Development/Video_Kit/zc702-zvik-camera/hardware/vivado/project/zvik_camera_2013.2.srcs/sources_1/bd/design_1/ip/design_1_fmc_imageon_vita_receiver_1_0/work/project_1.srcs/sources_1/imports/vita/afifo_64i_16o.vhd":120]

Opt Design
[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[2]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[3]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[4]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[5]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[6]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[7]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[8]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.demux_fifo_l/K7_GEN.afifo_64i_16o_k7_l (afifo_64i_16o_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/DEMUX_GEN.XSVI_10BIT_GEN.xsvi_video_data_o_reg[9]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/framestart2_regen_l/K7_GEN.pulse_regen_k7_l (pulse_regen_k7) is driving pin I0 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/HSyncState_s_reg[1]_i_1. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2785_5291_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2752_5014_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2749_4988_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2746_4962_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2743_4936_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2740_4910_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2737_4884_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2734_4858_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2731_4832_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2728_4806_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2725_4780_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2781_5260_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2722_4754_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2719_4728_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2716_4702_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2713_4676_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2710_4650_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2707_4624_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2704_4598_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2701_4572_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2698_4546_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2695_4520_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2777_5229_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2692_4494_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2689_4468_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2773_5198_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2770_5170_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2767_5144_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2764_5118_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2761_5092_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2758_5066_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2755_5040_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2712_4669_i_4. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_rxfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/ERROR_reg. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[0]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[10]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[11]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[12]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[13]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[14]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[15]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[17]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[18]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[19]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[20]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[1]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[21]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[22]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[23]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[24]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[25]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SpiRw_reg. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I0 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/SpiRw_reg_i_1. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[2]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I1 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/spi_seq_reg[0]_i_3. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I0 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/spi_seq_reg[3]_i_2. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[3]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[4]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[5]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[6]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[7]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[8]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin D of primitive cell design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi/the_spi_seq/SPI_DATA_TX_reg[9]. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I0 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/spi_seq_reg[2]_i_2. This blackbox cannot be found in the existing library.

[Opt 31-30] Blackbox design_1_i/fmc_imageon_vita_receiver_1/U0/USER_LOGIC_I/VITA_CORE_I/vita_spi_txfifo_l/K7_GEN.afifo_32_v6_l (afifo_32_k7) is driving pin I5 of primitive cell design_1_i/fmc_imageon_vita_receiver_1/i_2736_4877_i_4. This blackbox cannot be found in the existing library.

 

 

Anyone have the experience with these error before ? Please help me out.

 

Cheers guys,

 

Maxi.

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Xilinx Employee
Xilinx Employee
12,852 Views
Registered: ‎07-01-2010

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Hi Maxi,

Are you using 2013.2?
Can you try using 2013.3 as are similar issues seen in 2013.2 and fixed in 2013.3 or the latest version?

Regards,
Achutha
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Observer
Observer
12,788 Views
Registered: ‎02-05-2008

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Unfortunately, upgrading the version of the tools does not seem to solve the problem. I have installed Vivado 13.4 and while trying to follow the XAPP794 I've stumbled upon a few obstacles. First of all, the IPs added to the project by TCL file have new versions and I had to update them manually. I also had to change the name of the board by hand - that seems to have changed in the newer versions too. 

 

 

This gets me to the line 98 of the TCL:

 

# apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "iic_main" } [get_bd_intf_pins /iic_main/iic]
ERROR: [board_rule:/iic_main-101] Invalid Configuration value "iic_main" for "Board_Interface".
INFO: [BD 5-145] Automation rule xilinx.com:bd_rule:board was not applied to object IIC
INFO: [Common 17-17] undo 'endgroup'
INFO: [Common 17-17] undo 'startgroup'

while executing
"apply_bd_automation -rule xilinx.com:bd_rule:board -config {Board_Interface "iic_main" } [get_bd_intf_pins /iic_main/iic]"
(file "./scripts/build_camera_design.tcl" line 98)

 

And that's it. Seems like I will have to revert to 13.2 to get this up and running. I am now considering whether or not I should procure a number of virtual machines with all the Xilinx tool versions from the past two years installed :)

 

 

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Newbie
Newbie
12,691 Views
Registered: ‎02-12-2014

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

I am using vivado2013.3. After updated IPs' version, I got same error as sepher described above. Anyone solved it?
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Participant
Participant
12,589 Views
Registered: ‎10-23-2013

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Hi,

 

I also encounter the same problem using vivado 2013.2. Is there any more solution?

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Visitor
Visitor
12,446 Views
Registered: ‎11-19-2012

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

I'm not sure if this is of interest to anyone but we have an updated TCL for XAPP794 that runs on 2013.4.  We can generate a bitstream and get the XAPP to run.  But we are not sure that we configured everything properly and so have asked Xilinx to update the project themselves.

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Observer
Observer
11,472 Views
Registered: ‎04-18-2014

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

I'm using Vivado 2013.4 and I'd be very interested by your updated script. Is there any way you can provide it to me please ?

It would be greatly appreciated :)

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Newbie
Newbie
10,876 Views
Registered: ‎06-24-2014

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

I am also very interested in the update xapp794 TCL script for Vivado 2013.4. Could you provide me it please?
Best regards.
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Highlighted
Visitor
Visitor
9,639 Views
Registered: ‎05-28-2012

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Could u please email me the script as well please.  My email addr is wira@my-ms.com.

 

Best Regards

Wira

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Anonymous
Not applicable
5,807 Views

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

Dear all,

 

I had exactly same problems like you. There is only one reason for all of them. This is because you extracted the files in your desktop or any other places that has a long name. So, what should you do to solve these problems? (Please do the following steps exactly and carefully)

 

1. Redownload the xapp794.zip file. 

2. Cut it and paste it exactly on C:\ drive. Then right click on it and choose extract it here (Do not choose extract to xapp794\).

3. Go to C:\zc702-zvik-camera-2013.2-20130915-design\zc702-zvik-camera\hardware and cut vivado folder and paste it in C:\.

4. Run Vivado 2013.2. 

5. In Tcl console write cd C:/vivado

6. In Tcl console write source ./scripts/build_camera_design.tcl

 

So everything goes fine and you will have the bitstream as well. But if you go forward and get this error at the end of the work (On bit stream generation) : 

This design contains one or more evaluation cores for which bitstream generation is not supported.

It means that you don't have license for some cores. So, to solve this problem also, you need to get a license exactly based on the way that is explaind in the PDF- 1080p60 Camera Image Processing Reference Design page 43 - and do the above steps from the beginning (step 1). 

 

I hope it will be useful for you. 

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Newbie
Newbie
1,018 Views
Registered: ‎09-27-2017

Re: Xapp794 - 1080p60 Camera Image Processing Reference Design - Hardware Rebuilding errors !!

hi, dear,

 

could you please send me your 2013.4 tcl file-?

i can't resolve v_spc_1 license err....ㅜ.ㅜ

 

> trts10@hanmail.net

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