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8,288 Views
Registered: ‎12-07-2008

Xdm Exception

Hi all,

I have a project that works fine with ISE8.2, now I'm trying to port it to ISE10.1, but during the synthesis I got this error:

 

EXCEPTION:Xdm:Signal.c:173:$Id: Signal.c,v 1.14 2004/04/08 23:06:50 jdl Exp $ - Xdm_Exception::IllegalPinSignal signal '/COMPUTE_CALL_RANGE/SOURCE/COMPUTE_CALL_RANGE/Range_reg/Q<0>' is not a peer or child of pin '/COMPUTE_CALL_RANGE/SOURCE/COMPUTE_CALL_RANGE/Q/Q<0>'

Process "Synthesis" failed

 

I don't know what to do, and I prefer not changing the code because I didn't write it, I'm just mantaing this part.

 

Below I reported the entity that fails

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity COMPUTE_CALL_RANGE is
    generic(
        Nbit_Range : integer:=32
        );
    port( CLK : in std_logic;
        RESET : in std_logic;
        ENABLE : in std_logic;
       
        RANGE_IN : in std_logic_vector(Nbit_Range-1 downto 0);
        RETURN_RANGE : in std_logic_vector(Nbit_Range-1 downto 0);  
       
        CC_RANGE : in std_logic_vector(Nbit_Range-1 downto 0);
       
        CALL_COMMAND : in std_logic;
        RETURN_COMMAND : in std_logic;
        CONDITION_CALL_COMMAND : in std_logic;
       
        RANGE_OUT : out std_logic_vector(Nbit_Range-1 downto 0)
        );
end entity COMPUTE_CALL_RANGE;



architecture COMPUTE_CALL_RANGE_arch of COMPUTE_CALL_RANGE is
   
   
    component mux2to1
        generic(
            N_bit : INTEGER);
        port(
            IN0 : in std_logic_vector((N_bit-1) downto 0);
            IN1 : in std_logic_vector((N_bit-1) downto 0);
            SEL : in std_logic;
            MUX_OUT : out std_logic_vector((N_bit-1) downto 0));
    end component;
    --  for all: mux2to1 use entity WORK.mux2to1(mux2to1_arch);
   
   
   
    component le_reg
        generic(
            N_bit : INTEGER);
        port(
            CLK : in std_logic;
            D : in std_logic_vector((N_bit-1) downto 0);
            Q : out std_logic_vector((N_bit-1) downto 0);
            ENABLE : in std_logic;
            LOAD : in std_logic;
            RESET : in std_logic);
    end component;
    --  for all: le_reg use entity WORK.le_reg(behavioral);
   
   
    signal command_request : std_logic_vector(2 downto 0);
    signal sel_range_sum_input : std_logic;
   
    signal load_range_reg : std_logic;
    signal sel_range_reg_input : std_logic;
   
    signal  range_sum_out0 : std_logic_vector (Nbit_Range-1 downto 0);
    signal  range_sum_out1 : std_logic_vector (Nbit_Range-1 downto 0);
    signal  range_sum_out : std_logic_vector (Nbit_Range-1 downto 0);
   
    signal range_reg_in1 : std_logic_vector (Nbit_Range-1 downto 0);
   
    signal range_reg_input : std_logic_vector (Nbit_Range-1 downto 0);
    signal range_reg_out : std_logic_vector (Nbit_Range-1 downto 0);
   
    signal range_reg_reset : std_logic;
   
   
begin
   
    ---------------------------------------  CONTROLLER
    command_request <= ( CALL_COMMAND, RETURN_COMMAND, CONDITION_CALL_COMMAND);
    controller: process(command_request)
    begin
       
        sel_range_sum_input <= '0';
        sel_range_reg_input <= '0';
       
        load_range_reg <= '0';
       
        case command_request is
           
            when "100" =>       --CALL_COMMAND
            load_range_reg <= '1';
           
            when "010" =>       --RETURN_COMMAND
            load_range_reg <= '1';
            sel_range_reg_input <= '1';
           
            when "001" =>       --CONDITION_CALL_COMMAND
            load_range_reg <= '1';
            sel_range_sum_input <= '1';
           
            when others =>     
            null;
           
        end case;
       
    end process;
   
   
    mux_range_reg: mux2to1
    generic map(
        N_bit => Nbit_Range)
    port map(
        IN0 => range_sum_out,
        IN1 => range_reg_in1,
        SEL => sel_range_reg_input,
        MUX_OUT => range_reg_input
        );
   
   
    --------------------------------------  RANGE SUB
    range_reg_in1 <= range_reg_out - RETURN_RANGE;
   
   
    --------------------------------------  RANGE SUM
    --      range_sum 0
    range_sum_out0 <=  range_reg_out + RANGE_IN;
    --      range_sum 1
    range_sum_out1 <=  range_reg_out + CC_RANGE;
   
    mux_range_sum: mux2to1
    generic map(
        N_bit => Nbit_Range)
    port map(
        IN0 => range_sum_out0,
        IN1 => range_sum_out1,
        SEL => sel_range_sum_input,
        MUX_OUT => range_sum_out
        );
   
    ---------------------------------------  RANGE REGISTER
    Range_reg: le_reg
    generic map(
        N_bit => Nbit_Range)
    port map(
        CLK => CLK,
        D => range_reg_input,
        Q => range_reg_out,
        ENABLE => ENABLE,
        LOAD => load_range_reg,
        RESET => range_reg_reset
        );
   
    range_reg_reset <= RESET;
   
    ---------------------------------------  OUTPUT
    RANGE_OUT <=    range_sum_out;
   
   
end COMPUTE_CALL_RANGE_arch

 

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5 Replies
Xilinx Employee
Xilinx Employee
8,265 Views
Registered: ‎11-28-2007

Re: Xdm Exception

Hi,

 

I think I have seen a similar problem before. that code also worked in a previous version of ISE, but failed in 10.1 with exactly the same error message.

if you want to solve it yourself ASAP, then I would suggest to put the "le_reg" module code in this COMPUTE_CALL_RANGE entity.

actually, comparing your code and the other code, it wouldn't even surprise me if just changing all Q names to something else (something like Q_out)  would solve the issue.

 

I would definitely recommend to open a webcase and refer to the CR476203 and webcase743704 to make sure your problem is fixed in ISE.

 

 

best regards,

Dries

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8,253 Views
Registered: ‎12-07-2008

Re: Xdm Exception

I ported the code of LE_REG inside the entity (it's just a register), but it still doesn't work

 

EXCEPTION:Xdm:Signal.c:178:$Id: Signal.c,v 1.14.328.1 2008/06/06 17:05:38 jdl Exp $ - Xdm_Exception::IllegalPinSignal signal '/COMPUTE_CALL_RANGE/SOURCE/COMPUTE_CALL_RANGE/mux_range_reg/IN0<0>' is not a peer or child of pin '/COMPUTE_CALL_RANGE/SOURCE/COMPUTE_CALL_RANGE/range_reg_out/D<0>'

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Xilinx Employee
Xilinx Employee
8,231 Views
Registered: ‎11-28-2007

Re: Xdm Exception

Hi,

 

I would even further unroll the code of this LE_REG.

it seems there is a subblock inside LE_REG called "range_reg_out". would it be possible to put also this code inside the entity?

or if it's a primitive, infer the register?

 

something like: 

process (C)
begin

if (C'event and C='1') then
if (S='1') then
Q <= '1';
else
Q <= D;
end if;
end if;

end process;

 

again, it would be best to open a webcase so that this is investigated further and it is made sure that ISE is fixed for this problem.

 

 

best regards,

Dries

--------------------------------------------------------------------------------------------------------------------
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8,163 Views
Registered: ‎12-07-2008

Re: Xdm Exception

LE_REG is a simple register with asynchronous reset,load and enable, there is nothing to unroll unfortunately.

I discovered something, the code I posted is part of a bigger project, if i synthesize it by setting it as Top Module I get the error, but if I create a brand new project with just these files ... then there is no error.

I opened a webcase (<CASE:766635>) but we got stuck because I'm not able to recreate the error on a smaller project.

 

 

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Visitor girardeyr
Visitor
7,092 Views
Registered: ‎05-06-2009

Re: Xdm Exception

Hi,

 

I have exactly the same problem. I work with ISE and EDK 10.1 SP3.

I made a project which works fine.

But as soon as I configure Xst to "keep Hierarchy" I get this error:

EXCEPTION:Xdm:Signal.c:178:$Id: Signal.c,v 1.14.328.1 2008/06/06 17:05:38 jdl Exp $ - Xdm_Exception::IllegalPinSignal signal '/rampgen/SOURCE/rampgen/i_ynow/q<0>' is not a peer or child of pin '/rampgen/SOURCE/rampgen/q/Q<0>'
There is something curious: I have a signal named "rampgen/i_ynow/q<0>" in my design, but not "rampgen/q/Q<0>"

Should I open a webcase, or there is an Answer anywhere?

Best regards

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