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Newbie
Newbie
7,509 Views
Registered: ‎04-30-2009

Xilinx 11.1 does not support TWB.... then how do I make Test Bench easily??

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I used Xilinx 10.1 instead of ModelSim

 

Because it was not only much more stable, easy to use than ModelSim but also support TBW....

 

 

It was pretty easy to make testbench file with just some clicks...

(My friend who use ModelSim make testbench files with every keyboard input...)

 

 

 

 

 

 

But after upgrade to 11.1, It's manual says they does not support TWB files any more.

 

So that means..... Is there no way to make testbench without any keyboard input??

 

(Ah... maybe one solution will be... downgrade to 10.1-_-;;)

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Historian
Historian
8,638 Views
Registered: ‎02-25-2008

armed23ogm wrote:
I am curious about this too.  I am just starting out in FPGA's and was a little confused on how to create a Test Bench.

Professional users do NOT create test benches with a waveform display that just toggles a couple of signals.

 

A real test bench will include bus-functional (and if necessary, timing) models of the peripherals to which the FPGA connects. For example, say you have a system with an ADC with SPI serial port, your FPGA doing some processing, and a DAC with some sort of digital interface.

 

The bad way of testing your FPGA's processing would have your test bench toggle the SPI data bits, bit-banging essentially, and looking at the output waveform created by your processor.

 

The correct way of doing this would be to create an ADC model that generates known test data (say, a counter), serializes it in SPI format so the FPGA can easily accept the data. Your DAC model could accept the data over the FPGA-to-DAC interface, validate that the data were transmitted correctly (meets set-up and hold time, clock time, etc), and then if you know the expected results of your FPGA processing, your DAC model could compare expected against actual and tell you if you pass or fail.

 

Sure, there is a lot of set-up time involved, and you have to obtain or write the models of the external logic, but you'll spend less time in the lab with an oscilloscope.

 

-a

----------------------------Yes, I do this for a living.

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Newbie
Newbie
7,418 Views
Registered: ‎05-10-2009
I am curious about this too.  I am just starting out in FPGA's and was a little confused on how to create a Test Bench.
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Historian
Historian
8,639 Views
Registered: ‎02-25-2008

armed23ogm wrote:
I am curious about this too.  I am just starting out in FPGA's and was a little confused on how to create a Test Bench.

Professional users do NOT create test benches with a waveform display that just toggles a couple of signals.

 

A real test bench will include bus-functional (and if necessary, timing) models of the peripherals to which the FPGA connects. For example, say you have a system with an ADC with SPI serial port, your FPGA doing some processing, and a DAC with some sort of digital interface.

 

The bad way of testing your FPGA's processing would have your test bench toggle the SPI data bits, bit-banging essentially, and looking at the output waveform created by your processor.

 

The correct way of doing this would be to create an ADC model that generates known test data (say, a counter), serializes it in SPI format so the FPGA can easily accept the data. Your DAC model could accept the data over the FPGA-to-DAC interface, validate that the data were transmitted correctly (meets set-up and hold time, clock time, etc), and then if you know the expected results of your FPGA processing, your DAC model could compare expected against actual and tell you if you pass or fail.

 

Sure, there is a lot of set-up time involved, and you have to obtain or write the models of the external logic, but you'll spend less time in the lab with an oscilloscope.

 

-a

----------------------------Yes, I do this for a living.

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Observer
Observer
7,240 Views
Registered: ‎11-12-2007

Hi bassman59,

 

Could you please provide a reference textbook or something else to learn about how to design and use bus functional models. Nowadays i hear about this topic man times but i could not find a reference for beginners.

 

Regards,

Anıl

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Historian
Historian
7,236 Views
Registered: ‎02-25-2008

anilcelebi wrote:

Hi bassman59,

 

Could you please provide a reference textbook or something else to learn about how to design and use bus functional models. Nowadays i hear about this topic man times but i could not find a reference for beginners.

 

Regards,

Anıl


Easy:

 

Janick Bergeron's "Writing Test Benches." I believe he's up to the 3rd edition. worth the money.

 

-a

----------------------------Yes, I do this for a living.
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Contributor
Contributor
6,862 Views
Registered: ‎06-24-2008
Also curious here.

I don't know much about systemverilog or verification in general and have been testing my components the "bad" way.  Do professionals generally verify designs in the same language (vhdl testbench to verify vhdl designs?) or do they mix and match? 

I am trying to learn more about verification an wanted to know if I should try to find an equivilent book in vhdl to the one bassman recommended or to learn systemverilog to test my vhdl designs.

Guidance/suggestions welcome
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