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Registered: ‎11-25-2014

Xilinx ALTSHIFT_TAPS equivalent?

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I need to port an existing design from an Altera Cyclone V device to Spartan-7. The design contains some filters where I used an Altera Megafunction called ALTSHIFT_TAPS. This is a RAM-based shift register with the ability to output taps at multiple points in the shift register chain (the number of taps and distance between them is selectable).

 

I see that Xilinx has a RAM-Based Shift Register IP core but I don't see the ability to access intermediate taps. Anyone familiar with ALTSHIFT_TAPS and know if there's a Xilinx equivalent?

Thanks,
Bob

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Mentor
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Registered: ‎02-24-2014

Re: Xilinx ALTSHIFT_TAPS equivalent?

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There's no real equivalent, but this doesn't sound very difficult to just rewrite in RTL.    How many taps do you need?  I can probably cook up something in VHDL if you don't mind a European flavor to the code.   :)

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Registered: ‎02-24-2014

Re: Xilinx ALTSHIFT_TAPS equivalent?

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There's no real equivalent, but this doesn't sound very difficult to just rewrite in RTL.    How many taps do you need?  I can probably cook up something in VHDL if you don't mind a European flavor to the code.   :)

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

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Registered: ‎11-25-2014

Re: Xilinx ALTSHIFT_TAPS equivalent?

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Thanks for the quick response, and for the VHDL offer (no need). I have a couple of these - one with 4 taps and another with 6. I agree it's not a difficult function to replicate, but using RAM with taps is very efficient resource-wise. To get the equivalent I'll have to either use multiple chunks of RAM or all registers.

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Registered: ‎02-24-2014

Re: Xilinx ALTSHIFT_TAPS equivalent?

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I think that Xilinx does a better job of this, because of the distributed ram elements...   take a look at these results:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity generic_shift_taps is
generic (
    number_of_taps : natural := 4;                      -- MUST be set
    tap_distance : natural := 16;
    width : natural := 1
    );
port(
    clk         : in std_logic;
    clk_en      : in std_logic := '1';
    shiftin     : in std_logic_vector(width-1 downto 0);
    shiftout    : out std_logic_vector(width-1 downto 0);
    taps        : out std_logic_vector(width*number_of_taps-1 downto 0)
    );
end entity;

architecture Behavioral of generic_shift_taps is
type t_shift_vector is array(natural range <>) of std_logic_vector(width-1 downto 0);
signal shift_vec : t_shift_vector(0 to number_of_taps * tap_distance - 1) := (others => (others => '0'));
begin
process(clk) is
begin
    if rising_edge(clk) then
        if clk_en = '1' then
            shift_vec <= shiftin & shift_vec(0 to shift_vec'right-1);
            shiftout <= shift_vec(shift_vec'right);
            for i in 0 to number_of_taps-1 loop
                taps((i+1)*width-1 downto i*width) <= shift_vec((i+1)*tap_distance-1);
            end loop;
        end if;
    end if;
end process;
end Behavioral;

I did this one bit wide, with 4 taps that are 16 elements apart...   Look at the resulting schematic:

taps.png

If you squint, you can see the SRL16E shift registers... each is a special LUT cell.    Total delay is 64 cycles here.   This has always been one of the weaknesses of Altera.      It wouldn't be hard to implement RAM based delay, it's just a little more code for tap intervals that are really long, like 256 and above.

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