Showing results for 
Search instead for 
Did you mean: 
Registered: ‎03-16-2020

Zynq 7020 automatic code generation for peripheral drivers


I have started to develop software for the ZYNQ 7020 SoC. I have finished several tutorials and I have found that whenever I use some predefined block in the PL (for example GPIO controller) then associated software driver for that peripheral is automatically generated. My question is whether this is true only for predefined blocks or also for user developed blocks?

Tags (1)
0 Kudos
4 Replies
Registered: ‎03-16-2020

Re: Zynq 7020 automatic code generation for peripheral drivers

I have found answer. The source code of the driver for the user defined IP blocks is not generated automatically. It is responsibility of the IP block developer to prepare the driver. This driver can be automatically included during platform project generation in case the driver is accompanied with special tcl script. Another question which arises is how to prepare the tcl script?

Registered: ‎03-25-2019

Re: Zynq 7020 automatic code generation for peripheral drivers

Hi @Steven,

Please check the UG1118.

Best regards,
Please don't forget to reply, kudo and accept as a solution
0 Kudos
Registered: ‎03-16-2020

Re: Zynq 7020 automatic code generation for peripheral drivers

Hello @abouassi,

thank you for your reaction. Unfortunately I am not able to find the information I have been looking for in the document UG118. I have found in another source (please see the attached document in section 4.3 starting on page 117) that the process of creating custom drivers consists of following steps:

01) definition of driver interface in the .h module of C programming language (e.g. peripheral_axi_ip.h) 

02) implementation of the driver in the .c module of C programming language (e.g. peripheral_axi_ip.c)

      as far as the implementation of the driver it is necessary to use the same approach as Xilinx uses i.e. IP block is modeled by the C       language structure and so on

03) creation of .mdd file associated to the driver (mdd file name has to be exactly the same as is the driver name)

OPTION psf_version = 2.1;

BEGIN DRIVER peripheral_axi_ip

OPTION supported_peripherals = (peripheral_axi_ip);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION NAME = peripheral_axi_ip;


04) Creation of .tcl script associated to the driver. The purpose of this tcl script is to append symbolic constants related to my_peripheral into the xparameters.h file and also create .c module containig the configuration table (peripheral_axi_ip_g.c file).

proc generate {drv_handle} {

::his::utils::define_include_file $drv_handle "xparameters.h" "peripheral_axi_ip" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"

::hsi::utils::define_config_file $drv_handle "peripheral_axi_ip_g.c" "peripheral_axi_ip" "DEVICE_ID" "C_S00_AXI_BASEADDR"

::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "peripheral_axi_ip" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"

05) In case we have prepared all the above mentioned files it is time to create following directory structure:

->IP_BLOCKS (or whatever name)



           ->src (contains .c and .h file with implementation and interface of our driver along with the Makefile)

           ->data (contains .mdd file and .tcl file)

06) Now we have to modify Vitis IDE settings:

a) Window->Preferences, Xilinx->Software Repositories

     Local Repositories->New and set the path to the IP_BLOCKS

     Global Repositories->New and set the path to the IP_BLOCKS

     Rescan Repositories 

     Apply and Close

b) Open .spr file in the Vitis IDE, choose domain and board support package

    In the Board Support Package tab choose Modify BSP Settings ...

    choose drivers in the left pane and the table search for peripheral_axi_ip in the "Component" column

    Open the menu in "Driver" column and choose driver name (in our case peripheral_axi_ip)

    Click OK

I have followed the above mentioned steps and I have received following error message 

Error occurred while generating bsp sources for the domain 'TEST_DOMAIN'.
Failed to generate the bsp sources for domain.TEST_DOMAIN

Details: invalid command name "::his::utils::define_include_file"

ERROR: [Hsi 55-1545] Problem running tcl command ::sw_peripheral_axi_ip_v1_0::generate : invalid command name "::his::utils::define_include_file"
while executing
"::his::utils::define_include_file $drv_handle "xparameters.h" "peripheral_axi_ip" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR..."
(procedure "::sw_peripheral_axi_ip_v1_0::generate" line 2)
invoked from within
"::sw_peripheral_axi_ip_v1_0::generate peripheral_axi_ip_0"

ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()

Can anybody give me an advice how to resolve that? It is worthwhile to say that I my application is based on the FreeRTOS operating system and I have been usign Vivado and Vitis IDEs in version 2019.2. 


0 Kudos
Registered: ‎03-16-2020

Re: Zynq 7020 automatic code generation for peripheral drivers

I have found the solution. The problem is in above mentioned procedure. The correct approach is little bit different.

01) First of all it is necessary:

a) write the peripheral_axi_ip.c and peripheral_axi_ip.h custom driver related modules

b) prepare the Makefile (use some of the makefiles accompanying the Xilinx drivers)

c) create the tcl script (peripheral_axi_ip.tcl) with following content:

proc generate {drv_handle} {

xdefine_include_file $drv_handle "xparameters.h" "peripheral_axi_ip" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"

xdefine_config_file $drv_handle "peripheral_axi_ip_g.c" "peripheral_axi_ip" "DEVICE_ID" "C_S00_AXI_BASEADDR"

xdefine_canonical_xpars $drv_handle "xparameters.h" "peripheral_axi_ip" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"

02) Let the Vivado create the default drivers.

03) In Vivado IP packager replace content of the automatically generated .c, .h, .tcl and makefile by the content of your counterparts.

04) Based on generated .xsa file you can then generate the Vitis platform project which will contain your .c, .h files along with _g.c file with the configuration table for individual instances of your custom IP core.


0 Kudos